The Impact of Qubit Connectivity on Quantum Advantage in Noisy IQP Circuits

Leonardo Placidi, Enrico Rinaldi, Keisuke Fujii, Chen-Yu Liu

#572 of 2593 · Quantum Physics
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1467±31
10501750
64%
Win Rate
25
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14
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39
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Rating
5.5/ 10
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Abstract

Instantaneous Quantum Polynomial-time (IQP) circuits are a candidate for demonstrating near-term quantum advantage, as their sampling task is believed to be classically hard in the ideal theoretical setting under standard complexity-theoretic assumptions. In noisy implementations, however, this hardness can disappear once circuit depth exceeds a noise-dependent critical threshold. We show that qubit connectivity is a key parameter in this transition, since sparse architectures require additional routing to implement long-range interactions, thereby increasing compiled circuit depth. To make this explicit, we present a connectivity-aware analysis of compiled IQP circuits. For a fixed abstract IQP instance, different hardware connectivity graphs yield different compiled depths and thus different effective positions relative to the noisy-IQP simulatability boundary. We quantify this architecture-dependent shift using the compiled depth overhead and the corresponding simulatability margin. We combine analytic depth estimates for sparse geometries, including the two-dimensional grid, with native-gateset-aware compilation experiments across seven hardware-grounded experimental device models derived from publicly available topologies. To compare these device models under a unified empirical framework, we approximate the effective noise level primarily through reported two-qubit gate error rates. This lets us compare how much effective noise sparse and fully connected architectures can tolerate for the same position relative to the noisy-IQP simulatability boundary. Our results show that sparse connectivity requires a lower effective noise level to sustain the same margin relative to the noisy-IQP simulatability boundary, and they provide a quantitative framework for determining when compiled IQP experiments are likely to remain outside, or instead enter, the classically simulatable regime.

AI Impact Assessments

(3 models)

Scientific Impact Assessment

Core Contribution

This paper presents a connectivity-aware framework for analyzing when noisy Instantaneous Quantum Polynomial-time (IQP) circuits transition from being classically hard to simulate to being efficiently simulatable. The central insight is straightforward but practically important: sparse hardware connectivity graphs require SWAP routing to implement nonlocal interactions, inflating compiled circuit depth, which in turn pushes implementations closer to (or beyond) the noise-dependent simulatability boundary established by Rajakumar, Watson, and Liu (SODA 2025). The authors formalize this through a "simulatability margin" m(H) and "simulatability shift" S(H), quantifying how different hardware architectures move a fixed abstract IQP instance in the (noise, depth) phase diagram relative to the critical boundary.

The paper combines analytic depth estimates for 2D grid architectures with empirical compilation experiments across seven hardware-grounded device models (two fully connected trapped-ion-like, five sparse superconducting-like), using pytket for native-gateset-aware compilation.

Methodological Rigor

The methodology is sound in its basic structure but has several notable limitations:

Strengths in approach:

  • The separation of abstract circuit specification from compiled physical realization is clean and well-formalized (Equations 4-7).
  • The analytic depth bounds for 2D grids (Equations 8-11) correctly capture the Θ(√n) routing overhead scaling.
  • The empirical compilation across seven device models with native gate sets provides concrete, reproducible data points.
  • Testing four interaction patterns (dense, sparse, local, RHG) spans the relevant spectrum from worst-case to theoretically motivated instances.
  • Weaknesses:

  • The effective noise proxy p_eff(H) is approximated solely by published two-qubit gate error rates, which is a substantial simplification. The authors acknowledge this but the gap between this proxy and the actual Pauli noise parameter p in the theorem is potentially large and architecture-dependent. Idle errors, crosstalk, and SPAM errors—all of which correlate with connectivity and routing—are not captured.
  • The simulatability boundary from [8] involves suppressed constants and low-order terms (Equation 3 uses asymptotic notation), yet the phase diagrams plot specific operating points against this curve. The constant c in D*(p,k) = c/(p·ln(k/p)) is not rigorously determined, making the quantitative positioning of operating points relative to the boundary somewhat approximate.
  • Circuit sizes are small (n=16 for most experiments, up to n=127 for RHG on one platform). While the scaling trends are informative, the practical conclusions for near-term quantum advantage at competitive scales (hundreds to thousands of qubits) require extrapolation.
  • The compilation uses default pytket placement strategies; the authors note alternative strategies may yield different results but don't explore this systematically.
  • Potential Impact

    The paper addresses a genuine practical question: which hardware architectures are best positioned for IQP-based quantum advantage demonstrations? The framework connecting compilation overhead to simulatability boundaries is useful and could influence:

    1. Hardware architecture decisions: Quantitative evidence that fully connected architectures (trapped-ion) have a structural advantage for IQP sampling tasks over sparse architectures (superconducting).

    2. Quantum advantage experiment design: Practitioners designing near-term advantage experiments can use this framework to assess whether their compiled circuits remain in the "potentially hard" regime.

    3. Benchmarking methodology: The simulatability margin m(H) could complement existing metrics like quantum volume by incorporating circuit-family-specific hardness considerations.

    However, the impact is somewhat limited because: (a) the qualitative conclusion—that routing overhead hurts—is already widely understood; (b) the quantitative conclusions depend heavily on the noise proxy and asymptotic boundary, both of which have significant uncertainty; and (c) the analysis applies specifically to IQP circuits, though the authors note extensibility to other circuit families.

    Timeliness & Relevance

    The paper is timely. It builds on the 2025 SODA result by Rajakumar et al. establishing polynomial-time classical simulation of constant-depth noisy IQP circuits, and connects this theoretical result to practical hardware considerations. With multiple groups pursuing near-term quantum advantage demonstrations using IQP and related circuits (including the authors' own companion work [4]), understanding when compiled implementations remain in the hard regime is directly relevant.

    The paper also arrives amid active debate about the meaning and achievability of quantum advantage on NISQ devices, making its quantitative framework for assessing architecture-dependent advantage retention relevant to the community.

    Strengths & Limitations

    Key Strengths:

  • Clean formalization of a practically important but under-analyzed effect (connectivity → compilation depth → simulatability shift).
  • Comprehensive empirical evaluation across diverse hardware models with native gate sets.
  • The RHG lattice analysis at device-relevant scales (n=90, 127) provides the most compelling data, showing 5.3×–20.9× depth overhead for sparse architectures on a theoretically motivated hard instance.
  • The framework is extensible to other circuit families with known simulatability boundaries.
  • Notable Weaknesses:

  • The noise model is oversimplified; the gap between the two-qubit error rate proxy and the actual theorem parameter undermines quantitative conclusions.
  • The asymptotic constants in the simulatability boundary are not pinned down, so the phase diagrams should be interpreted qualitatively rather than as precise predictions.
  • The paper has a flavor of comparing specific commercial platforms, with results that appear to favor the authors' affiliated platform (Quantinuum/trapped-ion). While the analysis is technically sound, the framing and emphasis should be noted.
  • No experimental validation on actual quantum hardware; all results are classical simulations of compilation.
  • The paper does not consider error mitigation techniques, mid-circuit measurement, or other strategies that could modify the effective operating point.
  • Additional Observations

    The paper is well-written and structured. The figures effectively communicate the phase-diagram analysis and scaling trends. The connection between quantum volume-style thinking and IQP-specific hardness criteria is a useful conceptual bridge. The work would be strengthened by: (1) sensitivity analysis of the boundary constant c, (2) incorporating a richer noise model, and (3) validation against actual hardware execution data.

    Rating:5.5/ 10
    Significance 5.5Rigor 5Novelty 4.5Clarity 7.5

    Generated Apr 15, 2026

    Comparison History (39)

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