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RTL-Interact: Training EDA-Interactive Models for Multi-Task RTL Design

Wenxuan Shi, Yaoyu Zhu, Di Huang, Chongxiao Li, Xiaoyun Zhang, Muxin Song, Yutong Wu, Ziyuan Nan

Oct 30, 2026arXiv:2610.41225v1
cs.AI
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Scorecard· 16/16
6.5/10 impact

Solid, well-engineered unification of tool-integrated SFT and shaped GRPO for RTL with strong CVDP results and open release, but incremental in idea and with thin statistical support for several ablations.

Abstract

Large language models offer a promising route to register-transfer-level (RTL) design, but reliable implementations require checking and revision based on electronic design automation (EDA) tools' feedback. Existing RTL-specialized models often lack learned interaction with such EDA tools or rely on separate generation and repair components. We introduce RTL-Interact, a multi-task post-training framework that trains a single RTL-specialized model to generate RTL, construct task-appropriate EDA checks, and revise implementations using tool feedback. The framework combines automatically constructed multi-task demonstrations with staged supervision from chain-of-thought to tool-integrated reasoning. We further introduce Pattern-Aware Policy Optimization (PAPO) for multi-task reinforcement learning. PAPO augments Group Relative Policy Optimization with correctness-gated rewards that favor concise successful checking while rewarding effective revision, and uses task grouping to preserve coverage across objectives. On CVDP, RTL-Interact-32B achieves 48.7% weighted Pass@1 and 68.9% Pass@5, surpassing its teacher model, DeepSeek-V3.2, while RTL-Interact-8B achieves 44.9% weighted Pass@1. Additionally, we show that PAPO can reduce average tool calls by 63.8% while improving Pass@1. Both models also outperform all RTL-specialized baselines on VerilogEval v2 and RTLLM v2, demonstrating the effectiveness of our method.

AI Impact Assessments

(1 model)

Core Contribution

RTL-Interact trains a single RTL-specialized LLM (Qwen3-8B/32B base) to generate Verilog, write its own task-appropriate EDA checks (simulation testbenches, lint, synthesis analysis, equivalence checks), and revise designs from the tool feedback. It has three parts:

  • Multi-task TIR data. DeepSeek-V3.2 distills about 13.5K tool-interaction trajectories across generation, completion, and optimization, filtered by task-specific acceptance criteria.
  • CoT→TIR staged SFT.
  • Pattern-Aware Policy Optimization (PAPO). This is GRPO with a correctness-gated reward that adds +0.5 for a single successful self-check round (ISR), +0.2 for refinement success (FRS), and −0.2 for unsuccessful checking (US). It also uses task-group quotas (about 7:3 functional:optimization).

    • The framing is a useful one. Prior RTL RL work (CodeV-R1, ChipSeek) uses EDA tools only as reward oracles. Agentic workflows (MAGE, VerilogCoder) use tools only through prompting. OriGen and ChipMATE need separate generator and repair components. Here one policy learns inference-time tool use. The novelty is mostly a sensible combination of known ingredients applied to a new domain: TIR (ToRA/ReAct-style) plus GRPO with a shaped reward. The reward shaping and task grouping are modest, heuristic additions.

    Methodological Rigor

    Strengths:

  • Matched-token-budget SFT ablation (Table 1) with order comparisons (CoT→TIR 29.5% vs. TIR→CoT 25.5%, naive mix 28.2%, TIR-only 28.5%).
  • PAPO component ablations with identical initialization and data.
  • A separate direct-generation vs. fixed-failure revision diagnostic.
  • Decontamination via 15-gram overlap.
  • Hidden test benches are not exposed to the model.
  • Candid appendix notes, for example: no ablation against a tuned length penalty, the generation-only transfer run does not isolate causal effects, and Pass@5 drops in some categories.

    • Weaknesses:

  • The CoT→TIR gain over TIR-only is about 1 point on 302 problems with 5 samples, with no confidence intervals or seeds, so it is probably within noise.
  • The PAPO ablations (5.2 and 3.1 points Pass@1) are single runs.
  • The reward magnitudes (0.5/0.2/−0.2) are unablated.
  • The "pattern" reward is correlated with the final-correct gate, so the "63.8% tool-call reduction" is partly built into the reward by design. Without a tuned cost-aware baseline, one cannot attribute it to "pattern awareness".
  • The 100-task revision study draws failing candidates from trajectories that include a binary-reward RL checkpoint. It uses one sample per task, so differences such as 26 vs. 35 are about 9 tasks.
  • Baseline fairness is mixed. Baselines were given tools they were not trained to use, which is a fair control but not a tuned one. The teacher, DeepSeek-V3.2, gets only a 6-call budget. The 32B-over-teacher margin (48.7 vs. 46.7 Pass@1) is small and may be noise. Baselines are 7B–8B vs. 32B in places, and the claim "outperform all RTL-specialized baselines" is on Pass@1 only (SiliconMind and SFT variants sometimes win Pass@5).
  • Self-generated testbenches may be weak. The case study shows the SFT model running three redundant passing checks, and the RL model passing a testbench with a possibly different (HALF=(NUM_DIV−1)/2) formula, so the internal check quality is unverified.

    • Potential Impact

    The result is practically relevant to LLM-aided chip design. A small open model that approaches or surpasses frontier models on CVDP, with promised release of models, data, and code, would be a useful baseline and starting point. The tool-call efficiency analysis is a moderately interesting observation: RL shrinks tool use while increasing thinking, so the model internalizes verification. The recipe (teacher TIR distillation → staged SFT → pattern-shaped GRPO with task quotas) may transfer to other tool-grounded code domains (HLS, formal verification, analog netlists). But it is domain-specific, and the contributions are engineering-flavored rather than conceptual.

    Timeliness

    Agentic and tool-integrated RL is a hot area, and CVDP is a recent, harder benchmark than VerilogEval. Interest in LLM-for-EDA is high, so the paper arrives at the right time. The competing landscape is crowded (ChipMATE, ACE-RTL, SiliconMind, InCoder, and others, all 2026), so the lasting value depends on the released artifacts.

    Strengths

  • Unified single-model design, multi-task coverage including optimization with PPA proxies, and a sensible, honest information boundary (no hidden tests).
  • Strong CVDP numbers across five categories, plus VerilogEval and RTLLM.
  • Comprehensive appendices (prompts, hyperparameters, reward values).
  • Useful analyses of stage order and efficiency.

    • Limitations

  • Statistical robustness (single runs, no error bars).
  • Modest margin over the teacher, with potential evaluation-budget advantages for the proposed models.
  • Reward hacking and weak self-testbenches are not analyzed.
  • Module-level tasks only.
  • Teacher-bound data quality.
  • Data are derived from CodeV-R1's dataset and its equivalence checker, which is simulation-based rather than formal.
  • Some baselines (ChipMATE) are not on the same interface.
  • Generalization of PAPO beyond RTL is untested.

    • Other observations

    Reproducibility is relatively good given the stated release, detailed hyperparameters, and prompts, though the full scoring prompt is in a supplementary artifact. Compute is moderate for SFT (8×A100), but the RL with 30K-token rollouts and tool calls on 32B is heavier. Rewards of the form "1 + δ" are simple and easy to port.

    Rating:6.5/ 10
    Significance 6Rigor 6Novelty 5.5Clarity 7

    Generated Nov 2, 2026

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