Unlocking a fast adiabatic CZ gate and exact residual cancellation between fixed-frequency transmons using a floating tunable coupler
Angela Q. Chen, Xian Wu, Sarah Strong, Stefano Poletto
Abstract
Tunable couplers in superconducting qubit architectures enable strong qubit-qubit interactions for two-qubit gates while suppressing unwanted coupling during single-qubit operations. However, achieving low error rates for fast two-qubit gates remains challenging, as suppressing leakage and non-adiabatic errors typically requires specialized qubit, coupler, or pulse designs, often at the expense of an idling condition. In this work, we demonstrate that a symmetric floating tunable coupler provides a natural platform for fast, high-fidelity adiabatic controlled-Z (CZ) gates. Its favorable energy-level structure eliminates the conventional trade-off between rapid conditional-phase accumulation and adiabatic evolution while preserving exact cancellation of residual interaction at idling. This architecture exhibits intrinsic robustness to non-adiabatic transitions, even under simple flux modulation waveforms. To push performance at short gate durations, where maintaining adiabaticity becomes more challenging despite the favorable level structure, we introduce pulse-shaping techniques based on the instantaneous adiabatic factor that further suppress non-adiabatic errors. We experimentally realize a 24 ns adiabatic CZ gate with fidelity exceeding 99.9% and stable operation over several hours.
AI Impact Assessments
(3 models)Scientific Impact Assessment
Core Contribution
This paper demonstrates that a symmetric floating tunable coupler architecture naturally resolves a long-standing three-way trade-off in superconducting qubit systems: fast two-qubit gate operation, favorable energy-level ordering for adiabatic evolution, and exact cancellation of residual ZZ interaction at idling. Previous grounded tunable coupler architectures could achieve fast adiabatic CZ gates only in the non-straddling regime, where exact ZZ=0 is inaccessible. The key insight is that the symmetric floating coupler's energy-level structure places the |11,0⟩ state as the highest-energy level in the two-excitation manifold at idling, enabling an adiabatic trajectory free from anticrossings with unbounded growth of the dynamical phase rate ζ. This eliminates the need for complex multi-coupler designs or tunable qubits. The authors further introduce an adiabatically weighted pulse (AWP) shaping technique based on the instantaneous adiabatic D-factor, achieving a 24 ns CZ gate with 99.919±0.010% interleaved randomized benchmarking fidelity.
Methodological Rigor
The paper combines thorough theoretical analysis with careful experimental validation. The simulation framework uses QuTiP with realistic device parameters extracted from a joint fit of spectroscopy and dynamical phase data. The adiabatic factor formalism (Eq. 1) is well-motivated and provides quantitative predictions that are validated experimentally through leakage amplification measurements. The agreement between predicted peak intervals in leakage data and measured values confirms accurate characterization.
The benchmarking methodology is notably rigorous. The authors employ maximum likelihood estimation for randomized benchmarking data with proper binomial statistics treatment, Wilson confidence intervals (rather than Wald intervals that can extend beyond physical bounds), and Monte Carlo sampling for error propagation. This statistical care is commendable given the high-fidelity regime where standard Gaussian approximations break down.
The comparison between symmetric and asymmetric coupler architectures (Appendix B3) provides convincing evidence for the architectural advantage, showing that the asymmetric system's D-factor is nearly an order of magnitude larger near qubit frequencies. The leakage amplification experiments, including identification of first- and second-order non-adiabatic bleeding channels, demonstrate deep understanding of the error mechanisms.
However, some aspects could be strengthened. A detailed error budget decomposing contributions from incoherent errors, leakage, and residual non-adiabatic transitions is explicitly deferred to future work. The AWP optimization relies on Optuna with 6 tunable parameters, and it is unclear how reproducible the optimization is or how sensitive the final fidelity is to the optimization landscape.
Potential Impact
Immediate applications: The architecture uses fixed-frequency qubits (eliminating qubit flux noise) with a single flux-tunable coupler, making it attractive for scalable quantum processors. The absence of direct qubit-qubit coupling capacitance is significant for multi-chip architectures, as the authors note this enables inter-die coupling—directly relevant to modular quantum computing approaches.
Gate speed: A 24 ns CZ gate is competitive with the fastest demonstrated two-qubit gates in superconducting platforms while maintaining ZZ=0 at idling. This combination is particularly valuable for quantum error correction, where both fast gates and low idling errors are essential.
Broader influence: The adiabatic factor-based pulse shaping is a general technique applicable to other coupler architectures. The detailed analysis of first- and second-order non-adiabatic transitions provides a framework for understanding leakage in complex multi-level systems. The demonstration that the symmetric floating coupler resolves the speed-adiabaticity-ZZ trade-off may redirect architectural choices across the superconducting qubit community.
Timeliness & Relevance
This work addresses a critical bottleneck in scaling superconducting quantum processors. As quantum error correction demonstrations push toward larger codes, the simultaneous requirements of fast gates, low idling errors, and scalable connectivity become increasingly pressing. The ZZ=0 condition is essential for high-fidelity single-qubit gates in multi-qubit systems, and the ability to maintain this while achieving sub-30 ns two-qubit gates is timely. The use of alternating-bias assisted annealing for frequency targeting and the demonstration of stable operation over 8+ hours address practical deployment concerns.
Strengths
1. Architectural elegance: The solution requires no additional hardware complexity beyond a standard floating coupler design, unlike double-transmon or fluxonium coupler proposals.
2. Clear physical insight: The connection between energy-level ordering, adiabatic factors, and gate performance is presented with exceptional clarity.
3. Experimental validation of theory: Leakage amplification measurements directly confirm the predicted dominant non-adiabatic channels from D-factor analysis.
4. Stability: The 8.5-hour stability measurement (99.874% average fidelity with 0.018% standard deviation) demonstrates practical viability.
5. Statistical rigor: Proper treatment of binomial statistics in RB analysis.
Limitations
1. Single device: Results are from one qubit pair; scalability claims, while well-motivated by design considerations, are not experimentally demonstrated on a multi-qubit processor.
2. Missing error budget: The lack of a complete error decomposition makes it difficult to assess how much room for improvement remains and what the dominant error sources are.
3. Readout fidelity: Q1 readout fidelity of 85% is relatively low, potentially affecting benchmarking accuracy despite the use of three-state classifiers.
4. AWP complexity: The optimization involves 6 parameters plus Optuna plus brute-force search, which may not scale easily to processor-level calibration.
5. Coherence degradation: The significant drop in qubit coherence when the coupler is pulsed near qubit frequencies (T1 dropping from ~80μs to ~10μs) suggests that improvements in coupler coherence are essential for pushing fidelities further.
6. Slight idling offset: The experiments were run at ZZ=27.3 kHz rather than the exact ZZ=0 point due to readout limitations, somewhat undermining the zero-ZZ claim.
Generated Apr 8, 2026
Comparison History (56)
Paper 2 demonstrates real-time quantum error correction with an FPGA-based neural network decoder integrated into a superconducting quantum processor, addressing a critical bottleneck for fault-tolerant quantum computing—low-latency classical decoding. This has broader impact across the quantum computing field as real-time QEC is essential for all scalable quantum architectures. While Paper 1 presents an impressive high-fidelity CZ gate (99.9% in 24ns), it represents an incremental advance in coupler design. Paper 2's demonstration of closed-loop QEC with mid-circuit feedback opens pathways to practical fault-tolerant computation, impacting a wider community.
Paper 2 likely has higher impact: it reports an experimental 24 ns adiabatic CZ with >99.9% fidelity plus exact idle ZZ cancellation, directly addressing a central bottleneck in scalable superconducting quantum computing with near-term deployability. The combination of a specific hardware architecture (floating tunable coupler), demonstrated performance, and practical pulse-shaping is methodologically strong and broadly relevant to device engineering and quantum algorithm execution. Paper 1 tackles an important systems bottleneck (decoding scheduling) but appears more architecture/simulator-dependent and narrower in immediate cross-platform adoption than a high-fidelity hardware gate result.
Paper 1 demonstrates a concrete experimental achievement—a 24 ns CZ gate exceeding 99.9% fidelity with stable operation—addressing a critical hardware bottleneck in superconducting quantum computing. The combination of the floating tunable coupler architecture enabling both fast gates and exact ZZ cancellation resolves a long-standing trade-off, with immediate practical impact on quantum processor performance. Paper 2 addresses an important classical decoding scheduling problem but is primarily a simulation-based systems contribution with more incremental advances. Paper 1's experimental validation and fundamental hardware improvement give it broader and more lasting impact.
Paper 2 presents a major architectural breakthrough that reduces the physical qubit cost of breaking RSA-2048 by an order of magnitude (to ~100,000 qubits) using QLDPC codes. This has enormous implications for both quantum computing scalability and cryptographic security, affecting multiple fields including computer science, cryptography, and quantum engineering. While Paper 1 demonstrates an excellent incremental advance in two-qubit gate fidelity (99.9% CZ gate), Paper 2's impact is broader and more transformative—it fundamentally changes the resource estimates for practical fault-tolerant quantum computing and has immediate policy implications for post-quantum cryptography adoption timelines.
Paper 1 demonstrates a dramatic reduction in quantum computing overhead for a landmark computational problem (RSA-2048 factoring), reducing required physical qubits by an order of magnitude to ~100,000 using QLDPC codes. This has profound implications for cryptography, quantum architecture design, and the timeline to practical quantum advantage. While Paper 2 presents an excellent experimental advance in superconducting qubit gates (24ns CZ gate at 99.9% fidelity), it represents an incremental improvement in hardware components. Paper 1's architectural breakthrough has broader cross-field impact and greater urgency for security and computing paradigms.
Paper 1 demonstrates a record-high key rate (10.34 Mbps) for free-space CVQKD with a novel self-referenced passive state preparation scheme, addressing critical practical challenges in quantum communication. It combines theoretical innovation (equivalence proof via temporal-mode theory) with experimental demonstration under realistic conditions. While Paper 2 presents an impressive 99.9% fidelity CZ gate using a floating tunable coupler—an important incremental advance in superconducting quantum computing—Paper 1 opens a more broadly impactful pathway for practical quantum communication, with implications for satellite-based QKD and real-world secure communications, giving it higher potential impact.
Paper 2 likely has higher impact: it demonstrates a 24 ns CZ gate with >99.9% fidelity and exact residual ZZ cancellation in a fixed-frequency transmon architecture, directly addressing a central scalability bottleneck in superconducting quantum computing. The combination of architectural novelty (floating tunable coupler with favorable level structure) and experimentally validated, robust high-performance gating is broadly relevant to near-term fault-tolerant roadmaps and could be adopted across many hardware platforms. Paper 1 is strong for QKD networking and integration, but its impact is narrower and depends more on deployment conditions and security/standardization pathways.
Paper 2 demonstrates a 24 ns two-qubit CZ gate with >99.9% fidelity in superconducting qubits. Reaching this fidelity threshold is a critical requirement for fault-tolerant quantum computing on the current leading hardware platform. While Paper 1 represents a major fundamental milestone for photonic quantum scaling, Paper 2 offers more immediate, practical applications and near-term technological impact in the rapidly advancing field of superconducting quantum processors.
Paper 1 significantly advances superconducting qubit technology, the current leading platform for quantum computing. By achieving a 24 ns CZ gate with >99.9% fidelity, it crosses critical fault-tolerance thresholds while solving the trade-off between rapid phase accumulation and idling errors. This provides immediate, highly practical solutions for scaling mainstream quantum processors. While Paper 2 is an excellent milestone for photonic quantum tech, Paper 1's breakthrough has more immediate and widespread applicability in advancing near-term fault-tolerant quantum computers.
Paper 2 likely has higher near-term scientific impact: it reports an experimentally demonstrated 24 ns CZ gate with >99.9% fidelity and exact residual ZZ cancellation in a broadly relevant fixed-frequency transmon architecture, directly advancing a core bottleneck for superconducting quantum processors. The methodological rigor and immediate applicability to many platforms are strong, and the result is timely for scaling NISQ and early fault-tolerant systems. Paper 1 is innovative and important for LDPC-based fault tolerance, but depends on more specialized hardware co-design and shows modest simulated logical performance at small code size, making real-world uptake less immediate.