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MiniPIC: Flexible Position-Independent Caching in <100LOC

Nathan Ordonez, Thomas Parnell

cs.LGcs.AIcs.CL
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#3017 of 5669 · cs.LG
Tournament Score
1394±48
10501750
59%
Win Rate
10
Wins
7
Losses
17
Matches
Rating
6.5/ 10
Significance6.5
Rigor5.5
Novelty5.5
Clarity8

Abstract

Retrieval-augmented and agentic workloads repeatedly prefill recurring predictable structured inputs (which we call "spans") such as documents and code files. Yet, prefix caching in engines such as vLLM cannot reuse their KV entries unless they share identical prefixes with another request, while Position-Independent Caching (PIC) implementations within production-grade inference servers typically either require substantial server code changes or keep KV state outside the server, incurring host-to-device transfer overhead. We present Minimalistic PIC (MiniPIC): a minimal, flexible and fast vLLM design built from two ingredients: positional-encoding-free KV cache and user-controlled cache-reuse primitives. MiniPIC stores unrotated K vectors in the KV cache, applies RoPE to K tiles inside attention using per-request logical positions, and exposes three user-facing and token-level primitives: block-aligned padding, span separator (SSep), and prompt depend (PDep), that modify hashing behavior and effective block-level causal attention structure. With fewer than 100 lines of core-engine changes plus a custom attention backend, these primitives are sufficient to realize multiple PIC methods, including Block-Attention, EPIC, and Prompt Cache, within the same running vLLM instance, while natively integrating with KV cache CPU offload implementations. On 2WikiMultihopQA, MiniPIC with interleaved scheduling improves prefill throughput by 49% over baseline vLLM, reduces cached-span time-to-first-token by up to two orders of magnitude, preserves the linear prefill scaling of uncached spans, and incurs only 5.7% worst-case overhead.

AI Impact Assessments

(1 models)

Scientific Impact Assessment: MiniPIC

1. Core Contribution

MiniPIC addresses a concrete systems problem in LLM inference: how to efficiently reuse KV cache entries for recurring prompt segments (spans) that appear at different positions across requests. The key insight is that position-independent caching (PIC) can be achieved with minimal engine modifications by (1) storing unrotated K vectors in the KV cache and applying RoPE inside the attention kernel at serving time, and (2) exposing three user-facing special-token primitives (padding, SSEP, PDEP) that modify block-hashing behavior to control cache reuse.

The paper frames this as a separation-of-responsibilities problem: the inference engine provides position-free storage and hash-chain manipulation, while span layout, padding, and scheduling policies are delegated to the user or orchestration layer. This is a clean architectural decision that contrasts with prior approaches (SPNL's CIDRA algorithm, MEPIC's chunk cache coordinator) that embed substantial new subsystems within the engine.

2. Methodological Rigor

The experimental evaluation is focused but somewhat narrow:

Strengths in evaluation:

  • The throughput benchmark uses a substantial dataset (12,576 2WikiMultihopQA samples) with a realistic RAG structure (10 documents per sample).
  • Microbenchmarks isolate overhead components: the 5.7% worst-case overhead when PIC is disabled establishes that the position-free KV cache imposes minimal cost.
  • TTFT measurements across document counts demonstrate the scaling advantage clearly—up to two orders of magnitude improvement over baseline vLLM.
  • The comparison against SPNL (CIDRA) on the same workload is informative, showing 33% throughput improvement attributable to eliminating copy/reposition overhead.
  • Weaknesses in evaluation:

  • Only one dataset (2WikiMultihopQA) and one model (Tulu3-block-ft / Llama-3-8B scale) are evaluated. The generality claims would be stronger with diverse workloads and model sizes.
  • MEPIC could not be compared due to unavailable code, leaving a gap in the competitive landscape.
  • The accuracy implications of span-based approximate attention are acknowledged but not measured—this is a significant gap for a systems paper targeting production deployment.
  • The SPNL baseline runs on vLLM 0.10.2 while MiniPIC runs on 0.15.01; while the authors argue version effects are negligible based on single-request TTFT comparisons, batch scheduling and memory management differences across five major versions could matter.
  • No evaluation of cache pressure scenarios, eviction behavior, or memory utilization under varying span redundancy patterns.
  • 3. Potential Impact

    Practical impact (high): This work has immediate practical value for RAG and agentic LLM serving. The open-source implementation on IBM's vLLM fork, combined with the minimal 78 LOC core footprint, makes adoption straightforward. The fact that it composes with vLLM's existing CPU offload infrastructure is a practical advantage over external caching approaches.

    Systems design impact (moderate-high): The paper makes a compelling architectural argument that PIC should be decomposed into position-free storage (engine responsibility) and reuse policy (user/orchestrator responsibility). This principle could influence how future inference engines are designed, and could be adopted by SGLang, TensorRT-LLM, and other systems.

    Research impact (moderate): MiniPIC provides a common substrate on which multiple PIC algorithms (Block-Attention, EPIC, Prompt Cache) can be expressed through the same primitives. This could accelerate PIC research by lowering the implementation barrier. However, the algorithmic contribution is incremental—the idea of position-free KV caches exists in prior work (MEPIC, DeepSeek-V2).

    4. Timeliness & Relevance

    This paper is highly timely. RAG and agentic workloads are dominant deployment patterns for LLMs, and prefill cost is a major bottleneck as context lengths grow. The gap between academic PIC proposals and production-ready implementations is well-known, and MiniPIC directly addresses this. The growing adoption of vLLM as the de facto open-source inference server makes vLLM-specific contributions particularly impactful.

    5. Strengths & Limitations

    Key Strengths:

  • Minimality as a feature: The 78 LOC core change count is not merely a marketing claim but is rigorously tabulated with categorization (new functionality, routing, bug fixes). This reflects genuine architectural alignment with vLLM.
  • Correct identification of the root cause: The analysis of why positional KV caches create fundamental concurrency conflicts (memory races, copy cycles, amplification) is precise and well-motivated.
  • Composability: Native integration with CPU offload, support for multiple PIC methods through the same primitives, and compatibility with vLLM's existing scheduler are important practical properties.
  • Interleaved scheduling (ISPS): The barrier-free scheduling strategy provides a meaningful additional throughput gain (~9%) beyond the position-free cache alone.
  • Open-source availability with a specific commit reference enables reproducibility.
  • Key Limitations:

  • Safety model: The paper explicitly pushes correctness responsibility to the user—incorrect special token placement causes silent false cache hits. This is a meaningful production risk that the paper acknowledges but does not address.
  • Single-GPU evaluation only: No multi-GPU or disaggregated serving experiments, which are the realistic deployment targets for production RAG systems.
  • No accuracy evaluation: Span techniques inherently approximate full causal attention. Without measuring task accuracy degradation, the throughput gains cannot be properly contextualized.
  • Limited workload diversity: One dataset, one model, one hardware configuration.
  • Triton-only attention backend: The position-free RoPE implementation is written in Triton; extending to FlashAttention-2/3 CUDA kernels would require additional kernel work not demonstrated here.
  • Eviction vulnerability: The paper acknowledges that cached spans may be evicted before dependent prompts are scheduled, with no mitigation implemented.
  • Overall Assessment

    MiniPIC is a well-executed systems paper that makes a practical and architecturally clean contribution to LLM inference. Its main novelty lies not in any single technique (position-free KV caches, hash-chain manipulation, interleaved scheduling) but in their synthesis into a minimal, composable design that achieves strong performance with remarkably few lines of code. The evaluation, while limited in breadth, demonstrates clear advantages. The work is most impactful as a practical systems contribution rather than a fundamental algorithmic advance.

    Rating:6.5/ 10
    Significance 6.5Rigor 5.5Novelty 5.5Clarity 8

    Generated Jun 12, 2026

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