Quantum memory on a nanophotonic silicon chip
Stephan Rinner, Jonas Schmitt, Kilian Sandholzer, Andreas Reiserer
Abstract
Integrated photonic circuits offer great promise for quantum technologies. However, due to the rapid propagation of light, many envisioned applications require efficient on-chip quantum memories with a programmable delay, compact footprint, and high fidelity. Implementing this based on standard semiconductor processing technology is an outstanding challenge. Here, we realize such memories using erbium-doped silicon waveguides, fabricated as part of a multi-wafer project by a nanophotonic foundry. We demonstrate light storage with a bandwidth and a programmable delay exceeding in a device with a footprint of only , outperforming on-chip delay lines by many orders of magnitude. The phase of the read-out light field is preserved with a visibility of . The efficiency of can be improved in future devices through resonator enhancement and higher dopant concentrations. With this, the demonstrated approach will pave the way towards applications in photonic quantum computing based on scalable silicon processing technology.
AI Impact Assessments
(3 models)Scientific Impact Assessment: "Quantum memory on a nanophotonic silicon chip"
1. Core Contribution
This paper demonstrates the first quantum memory implemented in a foundry-fabricated silicon nanophotonic waveguide, using erbium dopants and the atomic frequency comb (AFC) protocol. The key novelty is the integration of a functional quantum memory into a commercially manufactured silicon-on-insulator (SOI) platform — a standard semiconductor processing technology. The device stores faint laser pulses with 44.2 MHz bandwidth, achieves programmable delays exceeding 1 μs in a footprint of only 1.5×10⁻² mm², and preserves phase coherence with 91.3% visibility.
The central problem addressed is the incompatibility between quantum memory materials and scalable semiconductor manufacturing. Previous AFC memories used bulk crystals or exotic waveguide materials (LiNbO₃, YVO₄, YSO) that are not CMOS-compatible. By using erbium-doped silicon — operating at telecom C-band wavelengths — fabricated in a multi-project wafer run, this work bridges a significant gap between quantum memory research and photonic integrated circuit manufacturing.
2. Methodological Rigor
The experimental methodology is sound and well-documented. The authors systematically characterize the Er:Si system before demonstrating memory operation: pulsed resonant fluorescence spectroscopy reveals a 352 MHz inhomogeneous linewidth (5× narrower than prior commercial samples), spectral hole burning demonstrates selective population transfer, and spin-lattice relaxation parameters are extracted via temperature- and field-dependent measurements. The AFC is prepared using a clever combination of EOM sidebands and AOM frequency shifts to generate 36 comb teeth.
The coherence measurement using interference between retrieved and reference pulses is a standard but appropriate method, yielding 91.3(30)% visibility — a meaningful demonstration of phase preservation. The analytical model for memory efficiency (Eq. 1) is rigorously derived from Maxwell-Bloch equations with clearly stated approximations, and the optical depth is extracted as the sole fit parameter with proper uncertainty estimation via resampling.
However, there are methodological limitations. The memory is tested with faint coherent pulses (~21,000 photons), not single photons. While this is standard for proof-of-concept demonstrations, it leaves open the question of performance at the quantum level. The efficiency calibration method — matching interference pulse attenuation — is clever but indirect.
3. Potential Impact
The demonstrated efficiency of 1.89×10⁻⁸ is extraordinarily low — roughly 8 orders of magnitude below useful thresholds. The authors are transparent about this and provide a detailed roadmap for improvement: optimized burn contrast (15× improvement), increased waveguide length (25×), higher dopant concentration, slow-light waveguides, and cavity enhancement. They argue that combining these approaches could reach the ~10% regime. While plausible in principle, achieving this would require simultaneous advances on multiple fronts, each presenting significant engineering challenges.
The most impactful aspect is the foundry compatibility. If efficiency can be improved to practical levels, this technology could integrate directly into existing silicon photonic quantum computing architectures (e.g., PsiQuantum, Xanadu), replacing bulky fiber delay lines. The telecom C-band operation is another significant advantage for networking applications.
The paper also contributes useful materials science data: spin-lattice relaxation parameters for Er:Si site A (Orbach and direct process coefficients), and evidence that reduced erbium concentration yields narrower inhomogeneous lines.
4. Timeliness & Relevance
This work is highly timely. Photonic quantum computing has seen major advances recently (PsiQuantum's Nature 2025 paper, Xanadu's GKP qubit generation), and the need for integrated quantum memories is widely recognized as a critical bottleneck. The paper explicitly addresses this gap. The demonstration that erbium in silicon — a material system that has been studied primarily for single-emitter applications — can function as a memory platform is a meaningful conceptual advance.
The concurrent development of integrated photonic memories in other platforms (YSO waveguides achieving millisecond storage and >80% cavity-enhanced efficiency) provides important context. These competing approaches currently outperform the Er:Si system by enormous margins in efficiency, but lack the foundry compatibility that is this paper's distinguishing feature.
5. Strengths & Limitations
Key Strengths:
Notable Limitations:
Overall Assessment
This paper represents an important proof-of-principle that quantum memory functionality can be realized in foundry-fabricated silicon photonics. The scientific contribution is the demonstration itself and the systematic characterization of Er:Si for memory applications. However, the enormous gap between current performance and practical requirements means this is primarily a stepping stone — its ultimate impact depends entirely on whether the proposed efficiency improvements can be realized. The work is well-executed and clearly presented, with appropriate honesty about limitations.
Generated Apr 2, 2026
Comparison History (90)
Paper 2 likely has higher impact because it demonstrates an on-chip quantum memory in foundry-fabricated silicon nanophotonics—an experimentally realized, scalable hardware capability with broad applications (quantum networking, photonic QC, sensing). Methodological rigor is supported by concrete measured metrics (bandwidth, delay, footprint, phase preservation) and a clear path to improvement. Paper 1 is highly novel and timely for fault-tolerant QC, but its impact hinges on assumptions about QLDPC-code implementation and architectural feasibility; it is more speculative and narrower to cryptanalysis/FTQC resource estimates.
Paper 2 demonstrates a critical hardware milestone: integrated on-chip quantum memory using scalable silicon processing technology. While its current efficiency is low, solving the delay and footprint challenges on a foundry-compatible platform directly addresses a major bottleneck in photonic quantum computing and quantum networks. Paper 1 offers a strong theoretical algorithm with exponential speedups, but Paper 2's tangible hardware advancement paves the way for immediate and scalable real-world quantum technology applications.
Paper 1 presents a critical hardware breakthrough by physically realizing a quantum memory on a standard silicon chip. This directly addresses a major bottleneck in scalable photonic quantum computing and networking. While Paper 2 offers a strong theoretical contribution with a novel quantum algorithm for solving DAEs, its practical impact relies on the future availability of fault-tolerant quantum computers. Paper 1's use of standard foundry processes provides an immediate, tangible pathway to scalable quantum technologies, giving it a higher and more immediate scientific and real-world impact.
Paper 2 demonstrates a highly scalable, practical solution to a major bottleneck in quantum technologies: on-chip quantum memory. By utilizing standard semiconductor processing (erbium-doped silicon waveguides), it offers a direct path to real-world applications in photonic quantum computing and quantum networks. While Paper 1 provides a rigorous and valuable theoretical framework for quantum reflectometry, Paper 2's experimental realization on scalable silicon platforms gives it significantly higher potential for broad scientific and technological impact.
Paper 2 likely has higher scientific impact: it demonstrates a tangible, on-chip quantum memory using foundry-fabricated erbium-doped silicon waveguides, addressing a key bottleneck for scalable photonic quantum technologies. The result is timely, hardware-enabling, and broadly relevant across quantum computing, networking, and integrated photonics, with clear metrics (bandwidth, >1 µs programmable delay, phase preservation) and a realistic path to improved efficiency. Paper 1 is innovative and application-driven, but its impact depends more on near-term quantum optimization utility and comparative baselines, and is narrower to optimization workflows.
Paper 2 addresses a fundamental bottleneck in quantum computing—qubit overhead in quantum error correction. By co-designing ultra-high-rate qLDPC codes for neutral atom arrays and demonstrating extreme logical error suppression (approaching the teraquop regime), it offers a highly practical and transformative path toward fault-tolerant quantum computation. While Paper 1 is an impressive experimental feat for on-chip quantum memory, its currently very low efficiency limits its immediate applicability compared to the architectural breakthroughs in Paper 2.
Paper 2 demonstrates the first quantum memory on a nanophotonic silicon chip using erbium-doped waveguides fabricated via standard foundry processes. This addresses a critical missing component for integrated photonic quantum technologies with enormous scalability potential through existing semiconductor infrastructure. While Paper 1 presents impressive cryogenic engineering for connecting superconducting quantum processors over tens of meters, Paper 2's innovation is more broadly impactful—it bridges quantum memory and silicon photonics, enabling applications across quantum computing, communication, and networking with CMOS-compatible fabrication, promising wider adoption and cross-field influence.
Paper 1 demonstrates quantum memory on a nanophotonic silicon chip using foundry-compatible fabrication, addressing a critical bottleneck for scalable photonic quantum computing. Despite low current efficiency, the integration with standard semiconductor processing is a landmark achievement with transformative potential for quantum networking and computing infrastructure. Paper 2 presents a useful ML framework for interpreting quantum data, but is more incremental in the interpretable ML space. Paper 1's hardware breakthrough has broader and more immediate implications for the quantum technology ecosystem.
Paper 1 demonstrates a concrete experimental breakthrough—quantum memory on a silicon nanophotonic chip fabricated using standard foundry processes—addressing a critical need in integrated quantum photonics. Despite low current efficiency, the scalable CMOS-compatible approach has immediate relevance for quantum computing and networking. Paper 2 presents a theoretical quantum algorithm for Navier-Stokes simulation that is intellectually interesting but faces significant practical barriers (current quantum hardware limitations, moderate Reynolds numbers only). Paper 1's experimental demonstration on a scalable platform gives it broader near-term impact across quantum technology.
Paper 1 demonstrates a breakthrough in quantum teleportation bandwidth by 4 orders of magnitude (100 MHz to 1 THz), completely bypassing electronic feedforward limitations through an all-optical approach. This represents a fundamental advance enabling terahertz-clock quantum computing. Paper 2 demonstrates quantum memory on silicon chips but with extremely low efficiency (10^-8), limiting near-term impact. While both are important, Paper 1's dramatic speed improvement in a core quantum computing primitive has broader transformative potential for quantum computing and quantum internet architectures.