Junction-Intrinsic Dissipation in Hybrid Superconductor-Semiconductor Gatemon Qubits

Scientific Impact Assessment

Core Contribution

This paper addresses a longstanding open question in hybrid superconducting qubit research: why do gatemon qubits (based on superconductor-semiconductor-superconductor, S-Sm-S, Josephson junctions) consistently exhibit relaxation times (T₁) far below state-of-the-art SIS transmons? The key innovation is a controlled co-fabrication strategy where gatemons and conventional transmons are placed on the same chip with nominally identical circuit layouts, gate dielectrics, and control lines. The only intentional difference is the Josephson junction itself. Through systematic loss budgeting and temperature-dependent T₁ measurements, the authors demonstrate that the dominant limitation is junction-intrinsic dissipation — not Purcell decay, spontaneous emission, dielectric loss, or thermally activated quasiparticles.

This is an important diagnostic result rather than a performance breakthrough. It narrows the search space for coherence improvements in hybrid qubits by definitively pointing to the junction as the bottleneck.

Methodological Rigor

The experimental design is well-conceived. The co-fabrication approach effectively controls for confounding variables — substrate losses, interface dielectrics, electromagnetic environment, and fabrication flow are shared between gatemon and transmon reference devices. This is a significant methodological improvement over prior studies where gatemons and transmons were fabricated on different substrates or with different material stacks, making it impossible to isolate junction-specific contributions.

The loss budget analysis is thorough, covering Purcell decay (Eq. 4), spontaneous emission through the optimized XYZ-style control line (Eq. 5), and internal dielectric loss (Eq. 6), with the co-fabricated transmons providing a direct extraction of Q_int ≈ 0.93 × 10⁶. The combined theoretical T₁ limit exceeds measured gatemon values by more than an order of magnitude, a convincing gap.

The temperature-dependent T₁ measurements are well-executed and follow the standard quasiparticle activation model (Eq. 8). The extracted superconducting gaps are comparable for S-Sm-S and SIS junctions (∆/h ≈ 48-55 GHz), which rules out a substantially reduced induced gap as the primary culprit. The key finding — that the difference resides in the temperature-independent rate Γ₀ — is clearly demonstrated.

However, there are limitations in rigor. The study includes only a modest number of devices (4 transmons, 8 gatemons across 4 chips), and statistical power is limited. The phenomenological quality factor Q_phenom ≈ 2.5 × 10⁵ is acknowledged as device-dependent, and no microscopic mechanism is identified. The authors appropriately note this is an effective parameter, but the lack of mechanism identification limits the actionable conclusions. The temperature-dependent measurements are shown for only two device pairs (main text and appendix), which constrains generalizability. Additionally, the paper exclusively uses full-shell InAs/Al nanowire junctions; it remains unclear whether the conclusions extend to other S-Sm-S platforms (e.g., 2DEG-based junctions, partial-shell nanowires).

Potential Impact

For the hybrid qubit community, this paper provides critical guidance: improving gatemon coherence requires engineering the junction itself — cleaner superconductor-semiconductor interfaces, suppressed subgap conductance, and potentially larger-gap superconductors — rather than optimizing the surrounding circuit. This redirects research effort toward materials science and interface engineering.

For the broader superconducting qubit community, the co-fabrication benchmarking methodology is valuable and transferable. The approach of using on-chip reference transmons as loss budget calibrators could be adopted for evaluating other novel junction types (e.g., graphene junctions, topological junctions).

For topological qubit research, where S-Sm-S junctions are central to proposals for Majorana-based qubits, understanding and mitigating junction-intrinsic dissipation is essential. This work underscores that even with epitaxial interfaces, significant excess dissipation persists.

The practical impact is somewhat limited by the absence of a solution — the paper identifies the problem but does not demonstrate a path to fixing it, though it does suggest plausible mechanisms (subgap conductance, interface imperfections).

Timeliness & Relevance

This is highly timely. Gatemon qubits are experiencing renewed interest due to their gate tunability (useful for quantum processor architectures) and connections to topological quantum computing. The persistent T₁ gap between gatemons and transmons has been a known but poorly understood problem. With transmons now reaching millisecond T₁ times, understanding why gatemons remain stuck at microseconds is increasingly urgent. The systematic, controlled approach fills a gap in the literature, where most previous gatemon studies focused on demonstration rather than loss analysis.

Strengths

1. Elegant experimental design: Co-fabrication with identical layouts is the right experiment to isolate junction-specific loss.

2. Comprehensive loss budget: Quantitative accounting of all standard loss channels with transmon-calibrated benchmarks.

3. Temperature-dependent measurements: First systematic temperature-dependent T₁ study for gatemons, providing strong evidence against thermal quasiparticle mechanisms as the primary limitation.

4. Clear presentation: The narrative is well-structured, moving logically from co-design to benchmarking to loss budget to temperature dependence.

5. XYZ-style gate line optimization: The engineering of the gate line to reconcile DC tunability with suppressed spontaneous emission is a useful practical contribution.

Limitations

1. No microscopic mechanism identified: The phenomenological Q_phenom captures the excess loss but doesn't explain it. The discussion of subgap conductance and interface quality is speculative.

2. Limited device statistics: Small sample sizes weaken statistical conclusions.

3. Single junction platform: Only full-shell InAs/Al nanowire junctions are studied; generalizability to other S-Sm-S platforms is uncertain.

4. Best gatemon T₁ still modest: The 9.1 μs best value does not push the state-of-the-art for gatemons significantly beyond prior reports (~30 μs).

5. No direct quasiparticle measurements: A Ramsey-based offset-charge experiment to measure x_ne directly is suggested but not performed.

Overall Assessment

This is a solid, well-designed experimental study that makes an important diagnostic contribution to the hybrid quantum device community. It convincingly demonstrates that junction-intrinsic dissipation is the dominant T₁ bottleneck in gatemons, providing clear direction for future materials and interface engineering efforts. While it does not resolve the underlying mechanism or demonstrate improved coherence, the controlled comparison methodology and the definitive localization of the problem to the junction represent meaningful progress.