Fast, High-Fidelity Erasure Detection of Dual-Rail Qubits with Symmetrically Coupled Readout
Jimmy Shih-Chun Hung, Arbel Haim, Mouktik Raha, Gihwan Kim, Ziwen Huang, Ming-Han Chou, Mitch D'Ewart, Erik Davis
Abstract
Erasure qubits are a promising platform for implementing hardware-efficient quantum error correction. Realizing the error-correction advantages of this encoding requires frequent mid-circuit erasure checks that are fast, high-fidelity, and scalable. Here, we realize erasure detection with a hardware-efficient circuit consisting of a single readout resonator dispersively and symmetrically coupled to both transmons of a dual-rail qubit. We use this circuit to demonstrate single-shot erasure detection in 384 ns with minimal impact on the dual-rail logical manifold, achieving a residual error per check of , with only induced dephasing per check, and an erasure error per check of . The high degree of matched dispersive readout coupling (-matching) within the dual-rail qubit code space also allows us to realize a new modality: time-continuous erasure detection performed in parallel with single-qubit gates. Here we achieve a median error per gate with error induced by erasure detection. This demonstrates a reduction in erasure detection overhead as well as a crucial ingredient for soft information quantum error correction. Together, these results establish symmetrically coupled dispersive readout as a fast, hardware-efficient, and scalable component for erasure-based quantum error correction using transmon dual-rail qubits.
AI Impact Assessments
(3 models)Scientific Impact Assessment
1. Core Contribution
This paper presents a hardware-efficient approach to mid-circuit erasure detection for transmon dual-rail qubits using a single symmetrically coupled readout resonator (SRO). The key innovation is engineering symmetric dispersive coupling between a shared readout resonator and both transmons of a dual-rail pair, achieving χ-matching (|χ_DR/χ| < 1×10⁻²) over a 600 MHz bandwidth. This enables the resonator to distinguish the erasure state |gg⟩ from the logical subspace {|0_L⟩, |1_L⟩} without inducing measurement-induced dephasing between logical states.
The paper demonstrates two operational modes: (1) discrete single-shot erasure detection in 384 ns with residual error of 6.0(2)×10⁻⁴ per check, and (2) a novel continuous parallel erasure detection mode performed simultaneously with single-qubit gates, achieving median gate error of 7.2×10⁻⁵ with <1×10⁻⁵ error contribution from the detection itself. The latter is a genuinely new capability not previously demonstrated.
2. Methodological Rigor
The experimental characterization is thorough and well-structured. The authors employ multiple complementary benchmarking approaches:
The analytical framework connecting χ-mismatch to measurement-induced dephasing (Eq. 2-4) is clean and provides clear design guidance through the selective darkening mechanism. The derivation showing how driving at Δ_d = -χ minimizes both dephasing and readout-induced erasure is a useful theoretical contribution.
One limitation is that the error budget leaves ~20% unaccounted for, and the induced bit-flip mechanism is not fully understood (potentially from measurement-induced state transitions to undetected leakage levels). The authors acknowledge this openly.
3. Potential Impact
Hardware efficiency: The SRO eliminates the need for dedicated ancilla transmons for erasure detection, representing significant savings in circuit complexity. The same resonator serves triple duty: erasure detection, logical readout, and leakage detection. For scaled-up quantum processors, this reduction in component count and control lines is substantial.
Continuous parallel erasure detection: This is arguably the most impactful new capability. It eliminates the time overhead of erasure checks entirely by performing them concurrently with gates. Beyond overhead reduction, the continuous measurement record provides soft information—probabilities rather than binary outcomes—which can be fed directly to QEC decoders for improved performance, as analyzed in prior theoretical work [17, 18]. This opens a new modality for quantum error correction.
Practical QEC implications: The demonstrated erasure noise bias of 42:1 (erasure-to-residual error ratio) is a key metric for erasure-based QEC. Combined with the observation that more frequent erasure checking further converts residual errors (evidenced by the improvement from 6.0×10⁻⁴ to 5.4×10⁻⁴ when using interleaved check information), this validates the erasure qubit paradigm.
Broad applicability: While demonstrated on transmon dual-rails, the symmetric coupling principle could inform readout designs for other dual-rail encodings (cavity-based, fluxonium-based).
4. Timeliness & Relevance
This work addresses a critical bottleneck in the erasure qubit ecosystem. While several groups have demonstrated erasure encoding and high-fidelity operations, the erasure check itself has been a persistent challenge—requiring either dedicated ancilla qubits (hardware overhead), long measurement times, or introducing significant errors. The SRO approach resolves all three simultaneously.
The timing is particularly relevant given concurrent developments: dual-rail qubits achieving logical entanglement [7], cavity dual-rails with erasure-detected measurements [8], and theoretical analyses showing benefits of increased erasure check frequency [33, 34]. This work provides the practical readout component needed to realize these theoretical advantages.
5. Strengths & Limitations
Key Strengths:
Notable Limitations:
6. Additional Observations
The paper's error budget analysis is exemplary for the field, clearly decomposing contributions and identifying that idling errors (not measurement-induced errors) dominate the residual error. This is important because it means improvements in transmon T₁ and measurement chain efficiency translate directly to better erasure check performance without requiring fundamental design changes.
The leakage detection capability (Appendix H) using modified classification thresholds adds practical value with no additional hardware cost, addressing the important problem of leakage accumulation in QEC circuits.
Generated Apr 20, 2026
Comparison History (44)
Paper 1 presents a crucial experimental advancement in quantum error correction, demonstrating fast, high-fidelity erasure detection for dual-rail transmon qubits. This directly addresses a major bottleneck in realizing fault-tolerant quantum computing, offering high potential for immediate real-world application and scalability. While Paper 2 provides profound theoretical insights into quantum dynamics, Paper 1's practical hardware implementation and timeliness in the rapidly advancing field of quantum computing suggest a higher immediate broader scientific and technological impact.
Paper 1 demonstrates concrete experimental advances in erasure detection for quantum error correction—a critical bottleneck for scalable quantum computing. It achieves record-low residual errors and introduces time-continuous erasure detection during gate operations, directly enabling hardware-efficient quantum error correction. Its immediate practical relevance to building fault-tolerant quantum computers gives it broader impact. Paper 2, while theoretically elegant in settling query complexities across access models, addresses a more specialized problem in quantum property testing with less immediate practical consequence.
Paper 1 demonstrates significant experimental advances in erasure detection for dual-rail qubits, achieving state-of-the-art fidelities and introducing time-continuous erasure detection during gate operations. This has direct, near-term impact on practical quantum error correction—a central challenge in quantum computing. Paper 2 provides elegant theoretical results settling query complexities for channel certification across access models, but its impact is more confined to quantum information theory. Paper 1's experimental innovations address a critical bottleneck in scalable quantum computing, giving it broader and more immediate scientific impact.
Paper 1 tackles a critical bottleneck in practical quantum computing: quantum error correction overhead. By demonstrating fast, high-fidelity erasure detection with minimal induced error, it provides a scalable, hardware-efficient solution. This advancement has immediate technological implications for realizing fault-tolerant quantum computers. While Paper 2 offers a valuable fundamental physics framework for cooperative emission, Paper 1's direct relevance to advancing quantum technologies gives it a broader and more immediate scientific and real-world impact.
Paper 1 addresses a critical and immediate bottleneck in quantum computing: hardware-efficient quantum error correction. By demonstrating fast, high-fidelity erasure detection for dual-rail qubits, it offers a tangible, scalable solution that directly advances the timeline for fault-tolerant quantum computing. While Paper 2 provides an elegant universal bound in quantum optics, Paper 1 has significantly higher potential for transformative real-world applications and broad technological impact.
Paper 2 demonstrates a concrete experimental advance in erasure detection for dual-rail qubits with record-level performance metrics, directly addressing a critical bottleneck in hardware-efficient quantum error correction. It introduces a novel time-continuous erasure detection modality performed in parallel with gates, which is a practical breakthrough. While Paper 1 contributes a useful theoretical framework for state complexity in the stabilizer formalism, Paper 2's experimental results have more immediate and broad impact on the rapidly advancing field of fault-tolerant quantum computing, with clear scalability implications.
Paper 1 presents a significant experimental breakthrough in quantum error correction by demonstrating fast, high-fidelity erasure detection with exceptionally low error rates. Hardware-efficient physical implementations of QEC with concrete empirical validation typically have a broader and more foundational impact than software-level compiler optimizations for specific architectures, as demonstrated in Paper 2, because they directly enable the physical realization of scalable fault-tolerant quantum computing.
Paper 2 presents a concrete, experimental breakthrough in quantum error correction, a critical bottleneck in realizing practical quantum computers. Its demonstration of fast, high-fidelity, and time-continuous erasure detection has immediate and highly significant real-world applications in scaling hardware-efficient quantum systems. Paper 1, while theoretically rigorous and broad in its approach to quantum reflectometry, lacks the immediate, transformative application to quantum computing scalability seen in Paper 2.
Paper 2 demonstrates a concrete experimental advance in erasure detection for dual-rail qubits with state-of-the-art fidelity metrics and a novel time-continuous detection modality. It addresses a critical bottleneck in hardware-efficient quantum error correction with immediately applicable results. Paper 1 provides valuable theoretical insight into barren plateaus and variational quantum algorithms, but its impact is more incremental—clarifying proof boundaries rather than opening entirely new capabilities. Paper 2's experimental results are directly relevant to near-term quantum computing hardware development and scalable error correction, giving it broader and more immediate impact.
Paper 2 addresses the critical challenge of implementing quantum LDPC codes on realistic hardware through a novel hardware-software co-design approach, combining programmable toric architectures with efficient routing algorithms. It bridges the gap between theoretically superior LDPC codes and practical superconducting hardware constraints, reducing long-range couplers from O(n) to O(√n). Its breadth of impact spans architecture design, error correction theory, and compilation, providing a practical roadmap for scalable fault-tolerant quantum computing. Paper 1, while demonstrating impressive experimental results for erasure detection, addresses a more focused component-level advance.
Paper 2 presents a crucial experimental advance in quantum error correction (QEC) using erasure qubits, directly addressing a major bottleneck in realizing fault-tolerant quantum computing. The demonstration of fast, high-fidelity erasure detection with minimal induced error has immediate, high-impact practical applications for scalable quantum hardware. While Paper 1 offers valuable fundamental insights into decoherence in many-body systems, Paper 2's tangible technological progress in a highly active and critical area gives it a broader and more immediate potential scientific impact.
Paper 2 demonstrates a concrete experimental advance in erasure detection for dual-rail qubits with impressive quantitative results (residual error ~6×10⁻⁴, minimal dephasing). It introduces a novel time-continuous erasure detection modality performed in parallel with gates, enabling soft-information QEC. The experimental validation, hardware efficiency, and scalability make it immediately impactful for the rapidly growing field of hardware-efficient quantum error correction. Paper 1 offers a useful theoretical improvement to syndrome extraction but is more incremental in comparison to the experimental breakthrough and new operational modality demonstrated in Paper 2.
Paper 2 addresses a critical bottleneck in scalable quantum computing: quantum error correction. By demonstrating fast, high-fidelity, hardware-efficient erasure detection, it offers immediate practical advancements toward fault-tolerant quantum computers. This direct technological application and high relevance to a major, fast-moving field gives it higher potential for broad scientific and real-world impact compared to the fundamental, theoretical many-body physics insights presented in Paper 1.
Paper 2 likely has higher impact: it introduces the first general in-situ magic state injection method applicable to arbitrary CSS qLDPC codes, addressing a central bottleneck for fault-tolerant, low-overhead quantum computing (non-Clifford resources). Its breadth spans many code families and architectures, with circuit-level simulations showing competitive logical injection error rates and reduced space overhead versus prepare-and-transfer and surface-code approaches. Paper 1 is a strong experimental advance for erasure-based dual-rail transmons, but is more hardware- and encoding-specific, with narrower cross-platform reach than a broadly applicable qLDPC injection primitive.
Paper 2 likely has higher impact because it reports a concrete, experimentally validated advance: fast (384 ns), high-fidelity mid-circuit erasure detection with quantified error budgets and a scalable hardware-efficient readout, plus continuous detection during gates—directly addressing a key bottleneck for practical quantum error correction. Its methodological rigor and immediate applicability to superconducting quantum processors make it timely and broadly relevant to fault-tolerant quantum computing. Paper 1 is a valuable roadmap with broad perspective, but surveys typically have less direct transformative impact than a demonstrated enabling technique.
Paper 1 provides a highly practical, experimental advancement in quantum error correction, a critical bottleneck for scalable quantum computing. Its demonstration of fast, high-fidelity erasure detection with minimal dephasing directly impacts the near-term feasibility of fault-tolerant hardware. While Paper 2 offers profound theoretical insights into quantum circuit complexity, Paper 1's experimental results have more immediate, tangible applications and broader relevance across quantum engineering and experimental physics.
Paper 1 addresses one of the most critical bottlenecks in quantum computing: scalable, hardware-efficient quantum error correction. By demonstrating exceptionally fast, high-fidelity continuous erasure detection parallel to gate operations, it provides a crucial experimental breakthrough for fault-tolerant quantum computing. While Paper 2 offers a valuable algorithmic framework for hybrid quantum-classical simulations, Paper 1's foundational hardware advancements are more likely to dictate the trajectory of scalable quantum processor design, yielding a broader and more profound long-term scientific impact.
Paper 1 addresses quantum error correction, a critical bottleneck in scaling quantum hardware. By experimentally demonstrating fast, high-fidelity erasure detection, it offers immediate, practical advancements for building fault-tolerant quantum computers. Paper 2 provides a valuable mathematical proof of an algorithm's theoretical optimality, but Paper 1's experimental breakthrough has higher potential for immediate real-world application and broader impact on the active development of scalable quantum technologies.
Paper 1 demonstrates a significant hardware advance for quantum error correction with erasure qubits, achieving record-low residual errors and introducing a novel time-continuous erasure detection modality during gate operations. This directly addresses a critical bottleneck in scalable fault-tolerant quantum computing—a highly active and high-impact field. The results are immediately applicable to near-term quantum processors. Paper 2, while addressing an important gap in understanding strain effects on silicon vacancy centers, is more incremental in scope, characterizing known phenomena in a specific defect system rather than enabling a new capability.
Paper 2 demonstrates a concrete experimental breakthrough in erasure detection for dual-rail qubits with record-level performance metrics, directly advancing hardware-efficient quantum error correction—a critical bottleneck for scalable quantum computing. The novel time-continuous erasure detection modality and the exceptionally low error rates represent significant technical achievements with immediate practical implications. Paper 1 provides useful theoretical analysis for space-based quantum repeater mission design but is more incremental, comparing known approaches in a specific scenario without introducing fundamentally new concepts or experimental results.