Demonstrating Record Fidelity for the Quantum Fourier Transform
Philipp Aumann, Michael Fellner, David Alber, Max Cykiert, Christoph Fleckenstein, Roeland ter Hoeven, Leo Stenzel, Riccardo J. Valencia-Tortora
Abstract
We demonstrate the Parity Architecture on quantum hardware, using the quantum Fourier transform (QFT) as a benchmark. As a result, a record performance in both fidelity and qubit count is achieved using quantum processors with a native CZ-based instruction set. On the IBM Heron r3 chip, a process fidelity of the QFT algorithm of for qubits is achieved. The scaling of the speedup compared to previous swap-based methods is super-exponential . Furthermore, we show that the scaling can be improved further by including iSWAP gates in the instruction set.
AI Impact Assessments
(3 models)Scientific Impact Assessment
Core Contribution
This paper demonstrates a record-setting experimental implementation of the unitary quantum Fourier transform (QFT) on superconducting quantum hardware, achieving a process fidelity of ~10⁻² at N=50 qubits on IBM's Heron r3 processor. The key enabler is the Parity Twine Network (PTN) compilation method, which avoids SWAP gates by reorganizing computation around parity information, reducing two-qubit gate count by ~2/3 compared to the best prior SWAP-based methods (Fowler et al.). The paper additionally shows that using native iSWAP gates (on Rigetti Ankaa-3) can further halve the two-qubit gate count, reaching the theoretical asymptotic lower bound for all-to-all interaction circuits on a linear chain.
The central claim is a super-exponential speedup O(exp(N²)) in fidelity ratio over the best known alternative, which arises directly from the O(N²) reduction in two-qubit gate count — each gate contributing a multiplicative fidelity penalty.
Methodological Rigor
Benchmarking protocol: The process fidelity metric (Eq. 1) is well-established and follows the protocol of Bäumer et al. (2024), using m=20 initial states that map to known computational basis states under the QFT, with 2000 shots per circuit. This is a reasonable and previously validated approach for process-level benchmarking.
Fair comparison: Both Parity Twine and the Fowler baseline are run on the same hardware (ibmboston) with the same transpiler settings and dynamical decoupling, which strengthens the comparison. The authors also provide fixed-layout results (Appendix A) to control for layout selection effects, showing that the qualitative advantage persists.
Concerns about rigor:
1. The qiskit transpiler's layout optimization (level 3) introduces variability — the "sudden jumps" between data points (e.g., N=32 to N=34) are acknowledged but not fully controlled. While the fixed-layout appendix addresses this, the main results rely on transpiler-optimized layouts, which could inadvertently favor one method.
2. The plurality voting results (Fig. 3) are post-processed and, as the authors acknowledge, produce a skewed distribution that "should not be interpreted as a fidelity." The claim of "52-qubit record" using this metric is somewhat inflated since it conflates error mitigation with algorithmic performance.
3. The process fidelity of 10⁻² at 50 qubits, while a record, is still quite low in absolute terms — meaning the QFT output is largely noise-dominated. The practical significance of this threshold is not well justified.
4. The "super-exponential" speedup framing is mathematically correct (exponential of a quadratic in N) but somewhat misleading — it reflects the standard relationship between gate count reduction and fidelity, not a fundamental algorithmic speedup in computational complexity.
Potential Impact
Immediate practical impact: The Parity Twine method is directly applicable to any algorithm requiring dense qubit connectivity on sparse hardware topologies — this includes QAOA, Shor's algorithm subroutines, and other QFT-based algorithms. The demonstrated improvements are substantial and hardware-agnostic in principle.
Broader architectural implications: The result that iSWAP-based PTNs achieve the theoretical lower bound for two-qubit gate count on linear chains is significant for hardware design decisions. It provides concrete evidence that native iSWAP gates offer genuine advantages for certain circuit classes, which could influence future QPU instruction set design.
Compilation/software impact: If the Parity Twine compiler is released publicly (mentioned as forthcoming), it could become a standard tool in quantum circuit compilation, potentially displacing SWAP-network-based routing as the default for dense-connectivity algorithms.
Timeliness & Relevance
The paper is highly timely. The QFT has been recently proposed as a key performance indicator for quantum computing by the EU Quantum Flagship. The paper directly addresses the current bottleneck of connectivity-limited circuit execution on NISQ and early fault-tolerant devices. With IBM and Rigetti continuously improving hardware, demonstrating that compilation techniques can extract significantly more performance from existing devices is of immediate practical value.
Strengths
1. Clear, large-scale experimental demonstration on two different hardware platforms (IBM and Rigetti), establishing cross-platform applicability.
2. Significant quantitative improvement — extending the QFT from ~36 to ~50 qubits at the 10⁻² fidelity threshold is meaningful.
3. Theoretical optimality result — showing that iSWAP-based PTN achieves the lower bound on two-qubit gate count is a clean theoretical contribution.
4. Well-structured comparison against the established Fowler baseline with controlled experimental conditions.
Limitations
1. Incremental novelty: The Parity Twine method itself was introduced in prior work (Refs. 21, 29). This paper is primarily an experimental demonstration/benchmark, not a new algorithm or technique.
2. Limited hardware variety: Only two platforms tested, both superconducting. Ion-trap or neutral-atom demonstrations would strengthen generality claims.
3. No error analysis or uncertainty quantification: Error bars are absent from all figures, making it difficult to assess statistical significance of the improvements.
4. Plurality voting section is weak: The non-linear post-processing conflates algorithmic and mitigation improvements, and the comparison with prior 27-qubit ion-trap results is not apples-to-apples (different hardware, different era).
5. Absolute fidelities remain low: A process fidelity of 10⁻² means the algorithm output is 99% noise. The practical utility threshold for QFT-based applications is unclear.
6. No resource analysis for fault-tolerant regime: The implications for QEC-protected computation are not discussed.
Overall Assessment
This is a solid experimental demonstration paper that establishes a new benchmark for unitary QFT implementation on superconducting hardware. The super-exponential fidelity improvement over SWAP-based methods is convincingly demonstrated, though it follows straightforwardly from the known gate-count reduction. The paper's main contribution is validating the Parity Twine approach at scale on real hardware, rather than introducing fundamentally new concepts. It will be of interest to the quantum computing community, particularly those working on circuit compilation and hardware benchmarking.
Generated Apr 15, 2026
Comparison History (55)
Paper 1 demonstrates a landmark achievement in quantum simulation of a physically important model (Fermi-Hubbard) at unprecedented scale (120 qubits, 90 Trotter steps), directly observing spin-charge separation and achieving quantitative agreement with classical methods while demonstrating 3000× wall-clock speedup. It addresses a central problem in condensed matter physics and pushes the boundary of quantum utility. Paper 2, while achieving record QFT fidelity via the Parity Architecture, is primarily a benchmarking demonstration with narrower immediate scientific impact and less direct physical insight.
Paper 2 demonstrates a record-breaking hardware implementation of the Quantum Fourier Transform on 50 qubits. Since QFT is a fundamental building block for critical quantum algorithms like Shor's and phase estimation, achieving super-exponential speedup and record fidelity on actual hardware has immediate, widespread implications across quantum computing. Paper 1 presents an interesting but more niche theoretical vulnerability in distributed quantum machine learning.
Paper 2 demonstrates a concrete, record-breaking experimental result (QFT on 50 qubits with the Parity Architecture on real IBM hardware) with super-exponential speedup over swap-based methods. This has immediate, verifiable impact on quantum computing hardware benchmarking and circuit compilation. Paper 1, while theoretically interesting in combining Kuperberg's sub-cubic SK algorithm with randomized compilation, presents a more incremental and niche contribution with results on smaller-scale trapped-ion hardware. Paper 2's record fidelity claim and scalability demonstration on 50 qubits have broader and more immediate impact.
Paper 1 demonstrates a groundbreaking experimental achievement in quantum computing, achieving record fidelity and qubit count for the critical QFT algorithm on actual hardware. The demonstrated super-exponential speedup and practical validation on a 50-qubit system offer immediate and highly significant impact for the advancement of practical quantum algorithms, compared to the theoretical simulation of quantum networks presented in Paper 2.
Paper 1 likely has higher impact: it introduces a novel symmetry-aware quantum PINN framework (geometric inductive biases via equivariant generators and twirling) with broad applicability to PDE solving across scientific domains, and benchmarks against multiple baselines suggesting practical performance gains with fewer parameters. Its reach spans quantum ML, scientific computing, and physics/engineering applications, aligning with timely interest in symmetry-equivariant learning. Paper 2 is valuable experimentally but the reported QFT process fidelity (~1e-2) limits near-term utility; its impact is narrower (quantum architecture/benchmarking) despite strong scaling claims.
Paper 2 demonstrates a concrete, record-breaking experimental result (QFT with 50 qubits on real IBM hardware) using the Parity Architecture, achieving super-exponential speedup over swap-based methods. This has immediate, verifiable impact on quantum computing practice. Paper 1, while theoretically interesting in combining Kuperberg's sub-cubic SK algorithm with randomized compilation, presents a more incremental and niche contribution to gate synthesis. Paper 2's practical demonstration on state-of-the-art hardware, clear benchmark improvements, and broad applicability to quantum algorithms give it higher potential impact across the field.
Paper 1 demonstrates a tangible, record-breaking hardware implementation of the Quantum Fourier Transform on 50 qubits, a foundational algorithm for quantum computing. Its super-exponential speedup scaling marks a major near-term milestone. Paper 2 offers a valuable but theoretical, simulation-based architectural study for future quantum networks, lacking the immediate real-world breakthrough of Paper 1.
Paper 1 demonstrates a major empirical breakthrough on real quantum hardware for the Quantum Fourier Transform, a foundational quantum algorithm. The reported super-exponential scaling improvement and record fidelity at 50 qubits represent a significant milestone that could broadly accelerate practical quantum computing applications. While Paper 2 presents a valuable methodological advance in quantum machine learning for PDEs, Paper 1's hardware-proven results on a core algorithm offer broader, more immediate impact across the entire quantum computing field.
Paper 1 addresses a fundamental challenge in quantum information—quantifying multipartite entanglement with experimentally accessible observables. It provides general theoretical tools (bounds based on purities and correlation functions) applicable to arbitrary system sizes and multiple entanglement measures, with broad implications across quantum technologies. Paper 2 demonstrates an impressive engineering achievement (record QFT fidelity at 50 qubits), but the process fidelity of ~10^-2 is still very low, and the contribution is more incremental, focusing on a specific architecture optimization rather than establishing broadly applicable theoretical framework.
Paper 1 achieves a major hardware milestone by demonstrating the Quantum Fourier Transform on 50 qubits with record fidelity and a super-exponential speedup over previous methods. Given the QFT's central role in foundational quantum algorithms (e.g., Shor's algorithm, quantum phase estimation), this practical breakthrough has profound implications for accelerating the timeline of useful quantum computing. While Paper 2 provides valuable theoretical tools for quantifying entanglement, Paper 1's concrete, large-scale hardware demonstration will likely drive broader, more immediate technological advancements and applications across the field.
Paper 1 introduces a conceptually novel paradigm—using coherent superposition of spatially distinct noisy links to deterministically generate entanglement from separable states, effectively turning noise into a resource. This could broadly influence quantum communication, network architectures, and distributed entanglement engineering, with clear near-term experimental feasibility (interferometric setups). Paper 2 is a strong engineering/benchmarking advance for QFT on specific hardware, but its reported fidelity (~1e-2 at 50 qubits) limits immediate algorithmic utility and its impact is narrower, mainly within hardware compilation/architecture optimization.
Paper 2 is more conceptually novel and broadly impactful: using coherent superposition of communication links to deterministically generate entanglement (even leveraging noise as a resource) could reshape protocols in quantum networking, communication, and distributed quantum computing. It offers clear real-world applicability via interferometric implementations and extends to multipartite settings, increasing breadth. Paper 1 is a strong engineering/benchmarking advance for QFT on specific hardware, but the reported fidelity (~1e-2) limits near-term algorithmic utility and the impact is narrower and more platform-dependent.
Paper 1 demonstrates a major experimental breakthrough by achieving record fidelity at a 50-qubit scale for the Quantum Fourier Transform, a foundational algorithm for quantum advantage. Its super-exponential speedup over previous methods offers immediate, highly impactful real-world applications for scaling quantum hardware. While Paper 2 provides valuable theoretical insights into barren plateaus, Paper 1's tangible hardware results and direct applicability to core quantum algorithms give it a broader and more immediate scientific impact.
Paper 1 demonstrates a record-breaking performance for the Quantum Fourier Transform on actual quantum hardware at a significant scale (50 qubits). Because the QFT is a foundational component for many pivotal quantum algorithms, achieving a super-exponential speedup in scaling over previous methods provides a tangible, high-impact milestone for the field. Paper 2 offers interesting theoretical advancements in quantum machine learning, but Paper 1's concrete hardware results and direct applicability to core quantum computing algorithms give it higher immediate and broad scientific impact.
Paper 2 demonstrates a record-breaking experimental achievement on the Quantum Fourier Transform, a foundational algorithm for many quantum applications like Shor's algorithm. Scaling to 50 qubits with a super-exponential speedup over standard swap-based methods offers significant, immediate real-world impact for near-term quantum computing. While Paper 1 provides valuable theoretical insights into the barren plateau problem, Paper 2's tangible hardware results and broad algorithmic implications give it higher overall scientific impact and practical relevance.
Paper 1 represents a major experimental milestone, demonstrating the Quantum Fourier Transform with record fidelity on 50 qubits. The achieved super-exponential speedup over previous methods directly accelerates practical quantum computing applications, whereas Paper 2 offers theoretical unifications that, while rigorous, are narrower in immediate real-world technological impact.
Paper 2 likely has higher near-term scientific impact due to a concrete, hardware-demonstrated advance: record QFT fidelity at 50 qubits on a leading superconducting platform plus a compelling architectural compilation method with strong scaling claims and clear benchmarking. This is timely for NISQ-era quantum computing and broadly relevant to quantum algorithms, compilers, and hardware design. Paper 1 is conceptually unifying and mathematically valuable across open quantum systems and trajectories, but appears more incremental/abstract and may translate less directly into immediate experimental or technological milestones.
Paper 1 introduces a conceptual and methodological framework unifying classical and quantum tensor networks via a controllable post-selection “hyperparameter,” offering a broadly applicable idea for hybrid quantum–classical ML and potentially influencing both tensor-network theory and quantum ML practice. Its impact could extend across multiple subfields (quantum information, ML, tensor methods) and suggests new training/architecture design principles under realistic resource constraints. Paper 2 is timely and valuable as an engineering benchmark, but appears more incremental and hardware/platform-specific, with impact narrower to QFT implementation and compilation/architecture optimizations.
Paper 1 is more novel and potentially transformative: it proposes a new fault-tolerant architecture using QLDPC codes with dramatically reduced overhead, and provides concrete resource estimates that shift expectations for breaking RSA-2048—highly relevant to cryptography and quantum engineering. Its impact spans theory (codes/architecture), systems design, and security policy, and is timely given the push toward utility-scale fault tolerance. Paper 2 is valuable as an experimental benchmark, but the reported QFT process fidelity (~1e-2) limits near-term applicability, and the claimed scaling benefits are narrower in scope.
Paper 1 likely has higher impact: it proposes a novel, lower-overhead fault-tolerant architecture using QLDPC codes and quantifies a major cryptanalytic milestone (RSA-2048 factoring) with dramatically fewer physical qubits, directly affecting quantum architecture design, resource estimation, and security. Its potential real-world implications span fault tolerance, hardware roadmaps, and post-quantum cryptography policy. Paper 2 is an important experimental benchmarking advance, but the reported QFT process fidelity (~1e-2 for 50 qubits) limits near-term utility; its impact is narrower and more incremental.