This assessment is based on version 1 of this paper. Version 2 is now available on arXiv — the authors may have revised their methods, results, or conclusions.
A digitally controlled silicon quantum processing unit
Members of the HRL Quantum Team, Collaborators, :, Michael Abraham, Edwin Acuna, Tower S. Adams, Moonmoon Akmal, Matthew R. Alfaro
Abstract
Commercially-relevant quantum computers will require large numbers of high-performing qubits that can be manufactured, integrated, and controlled at scale. Silicon exchange-only (EO) qubits are a strong candidate modality due to their control-signal simplicity and compatibility with advanced semiconductor manufacturing, but questions remain around the achievability of sufficiently low noise and a scalable control and wiring solution. Here we introduce a quantum processing unit composed of a custom-designed cryogenic CMOS controller, a novel high-density superconducting ribbon cable, and a low-noise EO qubit device. The quantum chip features a three-rail array of 54 exchange-coupled quantum dots, configurable to host up to 18 EO qubits. We integrate and use these components to demonstrate qubit performance for both single-qubit and entangling operations that advances the EO state of the art by an order of magnitude. We further validate this system by implementing a distance-5 repetition code and a quantum error detecting code then make detailed comparisons with simulations. Our approach facilitates a utility-scale quantum computer with manageable operational and capital requirements.
AI Impact Assessments
(3 models)Scientific Impact Assessment
1. Core Contribution
This paper presents a fully integrated quantum processing unit (QPU) that combines three co-designed components: a custom cryogenic CMOS controller operating at 4 K, a high-density superconducting Nb/polyimide ribbon cable, and a 54-quantum-dot silicon chip configurable to host up to 18 exchange-only (EO) qubits. The central achievement is demonstrating that these components work together as a system, achieving single-qubit gate errors of 2×10⁻⁴ and CNOT errors of 3×10⁻³ (with best reproducible CNOT at 9×10⁻⁴) — an order of magnitude improvement over prior EO qubit results. The system is validated through implementation of distance-3 and distance-5 repetition codes and a [[4,2,2]] quantum error detecting code.
The key innovation is not any single component, but the systems integration philosophy: moving all time-varying control signals to a 4 K CMOS chip, using a superconducting ribbon cable to bridge to mK qubits, and demonstrating that this architecture does not degrade qubit performance. This directly addresses the "wiring bottleneck" — widely recognized as a critical scalability challenge for semiconductor spin qubits.
2. Methodological Rigor
The experimental methodology is thorough and multi-layered:
One notable weakness is the reliance on an "ersatz" quasi-static miscalibration parameter (Δθ/θ ~1.5%) to match simulation to experiment. While the authors are transparent about this, it means the dominant error source is not yet understood from first principles. The DEM analysis also reveals that this miscalibration model overestimates high-weight correlated errors, suggesting the real error structure is more benign but not fully captured.
3. Potential Impact
Near-term impact: This work fundamentally changes the scalability narrative for silicon spin qubits. By demonstrating that cryogenic CMOS control at 4 K can drive EO qubits at mK without performance degradation, it eliminates one of the most frequently cited objections to the platform. The power consumption of ≤3.5 W is within the budget of commercial dilution refrigerators, and the superconducting ribbon cable adds only ~10 μW thermal load to the mixing chamber.
Broader impact: The systems integration approach — wafer-fabricated controller, wafer-fabricated interconnect, wafer-fabricated qubit chip — establishes a manufacturing-compatible paradigm. The 200-mm foundry process, wafer-level probing for yield, and CNN-assisted automated tune-up all point toward industrialization.
For the QEC community: The [[4,2,2]] demonstration with F_L = 0.95 after three rounds (post-selected) and the distance-5 repetition code provide benchmarks directly comparable to superconducting and trapped-ion implementations. The DEM analysis showing no statistically significant unexpected high-weight events in the [[4,2,2]] code is particularly encouraging for scalability.
4. Timeliness & Relevance
This paper arrives at a critical juncture. Superconducting qubits (Google's Willow) and neutral atoms (multiple groups) have recently demonstrated QEC milestones, while silicon spin qubits have lagged in system-level demonstrations despite strong single/two-qubit metrics. This work closes that gap substantially. The concurrent progress from Intel and QuTech on silicon qubits using different architectures makes this a highly competitive moment, and the integrated control approach demonstrated here is a clear differentiator.
The EO qubit's all-electrical, all-baseband control (no microwave drives, no magnetic field gradients) is uniquely suited to cryogenic digital control, making this a natural pairing that other qubit modalities cannot easily replicate.
5. Strengths & Limitations
Key strengths:
Notable limitations:
Summary
This is a landmark systems-integration paper that advances the state of the art for silicon exchange-only qubits by an order of magnitude while simultaneously demonstrating a scalable control architecture. The dominant remaining challenges are engineering problems (signal integrity, magnetic hygiene, calibration automation) rather than fundamental physics limitations — a strong position for a technology approaching commercialization. The work credibly positions semiconductor spin qubits as competitive with superconducting and neutral atom platforms for fault-tolerant quantum computing.
Generated Apr 20, 2026
Comparison History (226)
Paper 2 has higher estimated scientific impact due to its strong real-world applicability and timeliness: it demonstrates an integrated, scalable hardware-control stack (cryo-CMOS, high-density wiring, and EO silicon qubits), improves gate performance by ~an order of magnitude, and validates with error-detecting/coding experiments—key steps toward utility-scale systems. The methodological rigor is high (system integration plus benchmarking vs simulations) and the impact spans quantum hardware, cryogenic electronics, and fault-tolerance engineering. Paper 1 is novel and rigorous theoretically, but its impact is more specialized and contingent on downstream adoption in practical algorithms.
Paper 1 likely has higher scientific impact due to its strong novelty in systems-level integration (cryogenic CMOS control + high-density superconducting cabling + scalable silicon exchange-only qubits), clear path toward large-scale, manufacturable quantum computing, and demonstrated advances in qubit/entangling performance plus error-detecting/repetition-code validation. Its real-world applicability and timeliness for utility-scale quantum computers broaden impact across quantum hardware, semiconductor engineering, and fault-tolerant architectures. Paper 2 is highly innovative for chiral/cascaded many-body quantum optics, but is more specialized and currently smaller-scale (four qubits).
Paper 1 demonstrates comprehensive system-level integration of a silicon quantum processing unit, including a cryogenic CMOS controller and up to 18 qubits. Its implementation of a distance-5 repetition code and quantum error detection marks a major leap for silicon-based quantum computing, which offers superior long-term scalability via advanced semiconductor manufacturing. While Paper 2 achieves impressive fidelity for superconducting qubits, Paper 1's end-to-end architecture and practical demonstration of error correction codes provide a more definitive pathway to utility-scale, fault-tolerant quantum computers, yielding higher long-term scientific and industrial impact.
While Paper 1 provides an innovative theoretical framework for quantum error correction, Paper 2 demonstrates a monumental experimental breakthrough in scalable quantum hardware. By successfully integrating a cryogenic CMOS controller, novel superconducting wiring, and a 54-dot silicon array hosting 18 qubits, Paper 2 directly addresses the most critical bottleneck in quantum computing: physical scalability. Its experimental validation of error correction codes on this architecture advances the state-of-the-art by an order of magnitude, offering immediate real-world applications and significantly accelerating the timeline toward utility-scale, commercially relevant quantum computing.
Paper 2 addresses scalable quantum computing—one of the most consequential technological challenges of our era. It demonstrates integrated cryogenic CMOS control, novel wiring, 54 quantum dots, order-of-magnitude performance gains, and error correction codes, directly advancing utility-scale quantum computers with broad commercial and scientific implications. Paper 1 is an elegant, novel first demonstration of an on-chip RF maser with strong sensing applications, but its impact is more specialized. Paper 2's breadth, industrial relevance, methodological rigor, and alignment with the intensely active race toward fault-tolerant quantum computing give it higher potential scientific impact.
Paper 1 presents a major system-level breakthrough by integrating an 18-qubit silicon array with a cryogenic CMOS controller and demonstrating quantum error correction. This represents a significant leap toward scalable quantum computing. While Paper 2 offers an innovative approach to on-chip photonic quantum memory, its exceedingly low efficiency limits immediate practical application. Paper 1's rigorous demonstration of a highly integrated, functional QPU addresses the critical quantum scaling bottleneck, giving it a substantially higher potential for immediate and broad scientific impact.
Paper 2 likely has higher scientific impact due to its direct path to scalable, manufacturable quantum computing: integrated cryo-CMOS control, high-density wiring, and an 18-qubit silicon EO platform with order-of-magnitude performance gains plus error-coding demonstrations. This is timely and broadly relevant across quantum hardware, semiconductor engineering, and fault tolerance, with clear real-world application potential. Paper 1 is highly novel and rigorous for 3D quantum dynamics simulation and will impact computational many-body physics, but it is more specialized and less immediately translational than a scalable QPU platform.
Paper 1 demonstrates a landmark breakthrough by scaling trapped atomic resources to the 10,000-qubit scale, a first across all quantum computing platforms. The highly novel use of a single macroscopic metasurface eliminates traditional optical bottlenecks, improving laser-power efficiency and allowing practical ex-vacuum operation. While Paper 2 offers excellent full-stack integration and error-detection for silicon qubits, Paper 1 represents a more fundamental paradigm shift in overcoming physical scaling limits. The cross-disciplinary integration of metasurfaces with atomic physics to achieve unprecedented scalability will likely drive broader scientific impact.
Paper 2 likely has higher impact due to its direct relevance to scalable, commercially viable quantum computing: it integrates qubits with cryogenic CMOS control and high-density wiring, demonstrates substantially improved gate performance, and validates system-level operation via distance-5 repetition and error-detecting codes. This combination of engineering integration, manufacturability, and error-correction demonstrations has broad cross-field implications (device physics, cryo-CMOS, packaging, architecture) and strong timeliness. Paper 1 is novel and valuable for bosonic state engineering in neutral atoms, but is earlier-stage and narrower in near-term deployment.
Paper 1 likely has higher scientific impact due to strong novelty plus clear, near-term applicability: an integrated silicon EO-qubit QPU with cryo-CMOS control, scalable wiring, improved gate performance, and explicit error-code demonstrations. It addresses key bottlenecks for utility-scale quantum computing (manufacturability, integration, control, noise) with concrete system-level engineering and validation, increasing timeliness and cross-field impact (quantum info, cryoelectronics, semiconductor manufacturing). Paper 2 is highly novel and potentially transformative, but its claims are earlier-stage and higher-risk with less immediate technological deliverability.