A digitally controlled silicon quantum processing unit
Members of the HRL Quantum Team, Collaborators, :, Michael Abraham, Edwin Acuna, Tower S. Adams, Moonmoon Akmal, Matthew R. Alfaro
Abstract
Commercially-relevant quantum computers will require large numbers of high-performing qubits that can be manufactured, integrated, and controlled at scale. Silicon exchange-only (EO) qubits are a strong candidate modality due to their control-signal simplicity and compatibility with advanced semiconductor manufacturing, but questions remain around the achievability of sufficiently low noise and a scalable control and wiring solution. Here we introduce a quantum processing unit composed of a custom-designed cryogenic CMOS controller, a novel high-density superconducting ribbon cable, and a low-noise EO qubit device. The quantum chip features a three-rail array of 54 exchange-coupled quantum dots, configurable to host up to 18 EO qubits. We integrate and use these components to demonstrate qubit performance for both single-qubit and entangling operations that advances the EO state of the art by an order of magnitude. We further validate this system by implementing a distance-5 repetition code and a quantum error detecting code then make detailed comparisons with simulations. Our approach facilitates a utility-scale quantum computer with manageable operational and capital requirements.
AI Impact Assessments
(3 models)Scientific Impact Assessment
1. Core Contribution
This paper presents a fully integrated quantum processing unit (QPU) that combines three co-designed components: a custom cryogenic CMOS controller operating at 4 K, a high-density superconducting Nb/polyimide ribbon cable, and a 54-quantum-dot silicon chip configurable to host up to 18 exchange-only (EO) qubits. The central achievement is demonstrating that these components work together as a system, achieving single-qubit gate errors of 2×10⁻⁴ and CNOT errors of 3×10⁻³ (with best reproducible CNOT at 9×10⁻⁴) — an order of magnitude improvement over prior EO qubit results. The system is validated through implementation of distance-3 and distance-5 repetition codes and a [[4,2,2]] quantum error detecting code.
The key innovation is not any single component, but the systems integration philosophy: moving all time-varying control signals to a 4 K CMOS chip, using a superconducting ribbon cable to bridge to mK qubits, and demonstrating that this architecture does not degrade qubit performance. This directly addresses the "wiring bottleneck" — widely recognized as a critical scalability challenge for semiconductor spin qubits.
2. Methodological Rigor
The experimental methodology is thorough and multi-layered:
One notable weakness is the reliance on an "ersatz" quasi-static miscalibration parameter (Δθ/θ ~1.5%) to match simulation to experiment. While the authors are transparent about this, it means the dominant error source is not yet understood from first principles. The DEM analysis also reveals that this miscalibration model overestimates high-weight correlated errors, suggesting the real error structure is more benign but not fully captured.
3. Potential Impact
Near-term impact: This work fundamentally changes the scalability narrative for silicon spin qubits. By demonstrating that cryogenic CMOS control at 4 K can drive EO qubits at mK without performance degradation, it eliminates one of the most frequently cited objections to the platform. The power consumption of ≤3.5 W is within the budget of commercial dilution refrigerators, and the superconducting ribbon cable adds only ~10 μW thermal load to the mixing chamber.
Broader impact: The systems integration approach — wafer-fabricated controller, wafer-fabricated interconnect, wafer-fabricated qubit chip — establishes a manufacturing-compatible paradigm. The 200-mm foundry process, wafer-level probing for yield, and CNN-assisted automated tune-up all point toward industrialization.
For the QEC community: The [[4,2,2]] demonstration with F_L = 0.95 after three rounds (post-selected) and the distance-5 repetition code provide benchmarks directly comparable to superconducting and trapped-ion implementations. The DEM analysis showing no statistically significant unexpected high-weight events in the [[4,2,2]] code is particularly encouraging for scalability.
4. Timeliness & Relevance
This paper arrives at a critical juncture. Superconducting qubits (Google's Willow) and neutral atoms (multiple groups) have recently demonstrated QEC milestones, while silicon spin qubits have lagged in system-level demonstrations despite strong single/two-qubit metrics. This work closes that gap substantially. The concurrent progress from Intel and QuTech on silicon qubits using different architectures makes this a highly competitive moment, and the integrated control approach demonstrated here is a clear differentiator.
The EO qubit's all-electrical, all-baseband control (no microwave drives, no magnetic field gradients) is uniquely suited to cryogenic digital control, making this a natural pairing that other qubit modalities cannot easily replicate.
5. Strengths & Limitations
Key strengths:
Notable limitations:
Summary
This is a landmark systems-integration paper that advances the state of the art for silicon exchange-only qubits by an order of magnitude while simultaneously demonstrating a scalable control architecture. The dominant remaining challenges are engineering problems (signal integrity, magnetic hygiene, calibration automation) rather than fundamental physics limitations — a strong position for a technology approaching commercialization. The work credibly positions semiconductor spin qubits as competitive with superconducting and neutral atom platforms for fault-tolerant quantum computing.
Generated Apr 20, 2026
Comparison History (178)
Paper 2 likely has higher scientific impact due to its strong real-world applicability and timeliness: it demonstrates an integrated, digitally controlled silicon QPU with cryo-CMOS control, scalable wiring, and substantially improved exchange-only qubit performance, plus validation via distance-5 repetition and error-detecting codes. This is methodologically rigorous engineering that directly addresses key bottlenecks for scalable quantum computing and could influence both academia and industry across hardware, control, packaging, and fault-tolerance. Paper 1 is conceptually novel for open-system simulation, but its near-term breadth and translational impact are less certain.
Paper 2 demonstrates a complete silicon quantum processing unit with integrated cryogenic CMOS control, 54 quantum dots, and order-of-magnitude advances in exchange-only qubit performance, including error correction codes. This represents a major experimental milestone toward scalable, commercially-relevant quantum computing using silicon—a platform compatible with existing semiconductor manufacturing. Its breadth of impact spans quantum computing hardware, semiconductor engineering, and error correction. Paper 1, while providing valuable theoretical convergence guarantees for SDP hierarchies, addresses a more specialized mathematical question with narrower immediate impact.
Paper 2 demonstrates a digitally controlled silicon quantum processing unit with 54 quantum dots, integrating cryogenic CMOS control, novel interconnects, and low-noise qubits—addressing the critical scalability challenge in quantum computing. It advances exchange-only qubit performance by an order of magnitude and validates with error correction codes. Its direct pathway toward commercially-relevant, utility-scale quantum computers using semiconductor manufacturing gives it broader and more immediate impact than Paper 1's squeezed light array, which, while novel, addresses a more specialized application domain.
Paper 2 likely has higher scientific impact because it demonstrates an integrated, scalable hardware stack (cryogenic CMOS control, high-density interconnect, and a 54-dot/18-qubit silicon EO device) with order-of-magnitude performance gains and on-chip error-correction/detection demonstrations. This directly targets key bottlenecks for utility-scale quantum computing—manufacturability, wiring, and control—making near-term real-world applications and cross-disciplinary influence (quantum + semiconductor engineering) strong. Paper 1 is highly novel and broadly relevant for biased-noise FTQC, but is more architectural/theoretical with platform proposals and simulations rather than a full system demonstration.
Paper 2 likely has higher impact due to substantial hardware-system innovation enabling scalable quantum computing: integrated cryo-CMOS control, high-density wiring, and improved exchange-only silicon qubit performance, plus demonstrations of error-detecting/correcting codes. This addresses a central bottleneck (scalable control/integration) with broad relevance across quantum engineering, semiconductor manufacturing, and fault-tolerant roadmaps. Paper 1 is innovative and timely for NISQ quantum chemistry, but is more domain-specific and its impact depends on near-term device-dependent sampling quality and generalizability.
Paper 1 demonstrates a major experimental advance in silicon-based quantum computing, integrating a full quantum processing unit with cryogenic CMOS control, 54 quantum dots, and order-of-magnitude improvements in exchange-only qubit performance including error correction demonstrations. This addresses critical engineering challenges for scalable quantum computing with immediate industrial relevance. While Paper 2 provides important theoretical bounds on entanglement distribution resources, Paper 1's experimental breakthroughs in a commercially viable qubit platform, combined with its systems-level integration approach, are likely to have broader and more immediate scientific and technological impact.
Paper 1 represents a major experimental milestone in quantum computing hardware, addressing critical scalability bottlenecks. By integrating cryogenic CMOS control with a 54-quantum-dot array and demonstrating quantum error correction, it provides a tangible pathway to utility-scale, commercially viable silicon quantum computers. While Paper 2 offers a significant algorithmic advance in computational chemistry, the hardware breakthroughs and real-world engineering impact of Paper 1 will likely drive broader technological transformation and command greater interdisciplinary attention.
Paper 1 demonstrates a complete, integrated silicon quantum processing unit with digitally controlled qubits, custom cryogenic CMOS, and novel interconnects—advancing exchange-only qubit performance by an order of magnitude and implementing error correction codes on real hardware. This represents a major experimental milestone toward scalable, manufacturable quantum computers with immediate industrial relevance. Paper 2 presents important theoretical advances in concatenated quantum error correction with novel ideas (Galois qudits, list decoding), but remains a theoretical/simulation study. The experimental demonstration and system-level integration in Paper 1 has broader and more immediate impact across quantum computing, engineering, and industry.
Paper 2 demonstrates a complete, integrated silicon quantum processing unit with cryogenic CMOS control, advancing exchange-only qubit performance by an order of magnitude and implementing error correction codes. Its impact is higher because it addresses the critical engineering challenge of scalable quantum computing using industry-compatible semiconductor manufacturing, with immediate implications for commercial quantum computers. While Paper 1 makes important theoretical contributions to concatenated quantum error correction with novel algebraic techniques, Paper 2's experimental demonstration of an integrated system with scalable architecture has broader and more immediate impact across quantum computing hardware, engineering, and industry.
Paper 2 claims a polynomial-time quantum attack that completely breaks newly standardized post-quantum cryptographic schemes (ML-KEM, Falcon, NTRU). If verified, this discovery would force a global redesign of post-quantum cryptography and have an astronomical impact on cybersecurity, mathematics, and computer science. While Paper 1 represents a significant step forward in scalable quantum computing hardware, breaking the world's leading cryptographic standards carries more immediate and widespread disruptive impact across multiple fields and real-world applications.
Paper 2 likely has higher impact due to its direct relevance to scalable, manufacturable quantum computing: integrating a silicon qubit array (up to 18 EO qubits), cryogenic CMOS control, and dense wiring addresses a key systems bottleneck. Demonstrating improved single- and two-qubit performance plus implementing a distance-5 repetition code and an error-detecting code strengthens methodological rigor and shows near-term applicability. Its breadth spans device physics, cryo-CMOS, packaging/interconnects, and quantum error correction, aligning with timely industry and academic priorities. Paper 1 is highly novel but more specialized and earlier-stage for applications.
Paper 2 demonstrates a more complete, scalable quantum computing system integrating custom cryogenic CMOS control, novel interconnects, and silicon qubits—addressing the critical engineering challenges of scaling quantum computers. Its order-of-magnitude improvement in exchange-only qubit performance, demonstration of error correction codes (distance-5 repetition code), and path toward utility-scale manufacturing using existing semiconductor infrastructure give it broader real-world impact. While Paper 1 presents elegant universal oscillator control via JC interactions with strong theoretical novelty, Paper 2's systems-level integration approach and silicon compatibility position it for more transformative near-term industrial impact.
Paper 1 represents a fundamental breakthrough in information theory, breaking the classical Shannon-Nyquist scaling limit for compressed sensing. By reducing the measurement bound to O(K) and experimentally validating this quantum approach, it offers transformative potential across diverse fields like imaging, communication, and signal processing. While Paper 2 is an impressive engineering achievement for scaling silicon quantum processors, Paper 1's paradigm-shifting theoretical innovation and broader interdisciplinary applicability give it a higher potential for widespread, cross-domain scientific impact.
Paper 1 presents a significant advancement in scalable quantum computing by demonstrating a functional silicon-based QPU with a cryogenic CMOS controller and error correction. Its compatibility with existing semiconductor manufacturing processes offers a clear path to commercially relevant, utility-scale quantum computers. While Paper 2 provides a remarkable milestone in precision measurement for fundamental physics, Paper 1 has far broader interdisciplinary implications, a clearer path to real-world technological applications, and aligns strongly with the immediate, high-impact goals of the quantum information science community.
Paper 2 demonstrates a fully integrated silicon quantum processing unit with cryogenic CMOS control, 54 quantum dots, and error correction codes—addressing the critical scalability challenge in quantum computing. Its compatibility with advanced semiconductor manufacturing, order-of-magnitude improvement in exchange-only qubit performance, and demonstration of a distance-5 repetition code represent a more transformative advance with broader industrial implications. Paper 1, while a meaningful first demonstration of quantum memory in TFLN, shows modest performance metrics (1.95% efficiency, 400 ns storage) and represents an incremental step in quantum memory research.
Paper 1 demonstrates a major experimental advance in silicon-based quantum computing, integrating a custom cryogenic CMOS controller with a 54-quantum-dot array and achieving order-of-magnitude improvements in exchange-only qubit performance, including error correction demonstrations. This represents a significant hardware milestone with direct implications for scalable, commercially relevant quantum computers. Paper 2 offers valuable theoretical improvements in fermion-to-qubit mapping overhead, but Paper 1's experimental integration of multiple novel components and state-of-the-art qubit performance addresses the critical engineering challenge of building practical quantum computers, giving it broader and more immediate impact.
Paper 1 has higher impact potential because it delivers a concrete, scalable hardware/control stack for silicon exchange-only qubits (cryo-CMOS controller, dense superconducting cabling, 54-dot array) and demonstrates improved gate performance plus error-detection/repetition-code experiments—directly advancing the path to utility-scale quantum computing with clear industrial relevance. Paper 2 is novel and timely for holography/quantum-simulation interpretation and offers practical circuit-cost reductions, but its impact is narrower and based on small-N numerical studies; it is more likely to reshape understanding within a subfield than enable broad real-world deployment.
Paper 1 demonstrates a major experimental advance in silicon-based quantum computing, integrating a cryogenic CMOS controller with a 54-quantum-dot array and achieving order-of-magnitude improvements in exchange-only qubit performance, including error correction demonstrations. This addresses critical scalability challenges for commercially relevant quantum computers using industry-compatible silicon fabrication. Paper 2 presents a theoretical contribution to distributed quantum metrology using punctured surface codes, which is intellectually interesting but narrower in scope and application. Paper 1's experimental integration of multiple novel components and its direct pathway to scalable quantum computing gives it substantially broader and more immediate scientific impact.
Paper 2 likely has higher impact due to its system-level advance toward scalable quantum computing: co-integrating cryogenic CMOS control, high-density wiring, and a multi-qubit silicon EO device, plus demonstrating error-detection/repetition-code operation. This directly targets manufacturability and control bottlenecks central to utility-scale machines, with broad implications across quantum hardware, cryo-electronics, and semiconductor integration. Paper 1 is novel and timely for telecom quantum networking, but its impact is more specialized to photonic memory performance and platform validation, whereas Paper 2 addresses a larger fraction of the full-stack scalability problem.
Paper 2 presents a major experimental breakthrough in scalable quantum computing, integrating silicon qubits with cryogenic CMOS control and demonstrating error correction. Its potential to overcome critical scalability bottlenecks in a highly transformative field gives it a higher estimated scientific and real-world impact compared to Paper 1, which primarily reviews theoretical and recent experimental progress in quantum optical imaging.