Heterogeneous architectures enable a 138x reduction in physical qubit requirements for fault-tolerant quantum computing under detailed accounting
Pranav S. Mundada, Aleksei Khindanov, Yulun Wang, Claire L. Edmunds, Paul Coote, Michael J. Biercuk, Yuval Baum, Michael Hush
Abstract
Quantum computer hardware is predicted to scale over hundreds of thousands of qubits coming online in the next decade. Despite significant theoretical and experimental QEC progress, quantum computer architecture has suffered a significant gap, with bottom-up physical-device-driven challenges largely disconnected from top-down QEC-code-driven considerations. In this work, we unify these two views, presenting a complete heterogeneous quantum computing architecture incorporating task-specific hardware selection and QEC encoding, and agnostic to code selection or physical qubit parameters. Our approach further enables special-purpose processing modules, and includes a full microarchitecture for fault-tolerant implementation of interfaces between quantum processing units and quantum memories. Using this architecture and a new fully featured compiler functioning across subsystems at the scale of logical qubits, we schedule and orchestrate a variety of algorithms down to hardware-specific instructions; a detailed accounting of all operations reveals up to 551x reduction in algorithmic logical error and up to 138x reduction in physical-qubit overhead compared to a monolithic baseline architecture. We then consider the factorization of 2048-bit RSA-integers; using an experimentally demonstrated grid-coupling topology, factoring RSA-2048 requires 381k physical qubits and 9.2 days, which can be reduced to 4.9 days via addition of an algorithm-specific accelerator for the Adder subroutine (requiring 439k qubits). Finally, assuming hypothetical long-range coupling, implementing quantum memory using qLDPC codes reduces the resources required for factoring to just 190k qubits and under 10 days. These results and the tooling we have built indicate that heterogeneous quantum-computer architectures can deliver significant, verifiable benefits on realistic hardware.
AI Impact Assessments
(3 models)Scientific Impact Assessment
1. Core Contribution
This paper presents Q-NEXUS, a heterogeneous quantum computing architecture that separates computation, communication, and storage into specialized modules, paired with Q-CHESS, a micro-architecture-aware compiler for end-to-end orchestration. The central insight is that quantum algorithms exhibit massive idling (e.g., ~96-97% of cycles in Shor's algorithm), and by offloading idle qubits to specialized memory modules—either static transversal quantum memory (STQM) using ultra-long-coherence qubits without active QEC, or random-access quantum memory (RAQM) with reduced-distance codes—one can dramatically reduce physical qubit overhead. The architecture supports heterogeneity in qubit modality, QEC code, and module function, analogous to the stored-program model in classical computing.
The headline results are: up to 138× reduction in physical qubits and 551× reduction in algorithmic logical error at the 1,000-logical-qubit scale, and RSA-2048 factorization requiring 381k physical qubits (grid topology) or 190k (with qLDPC codes in memory), both under 10 days runtime.
2. Methodological Rigor
Strengths in methodology:
Concerns:
3. Potential Impact
Immediate impact: This work reframes the quantum computing scaling challenge from "build bigger monolithic processors" to "architect heterogeneous systems with specialized modules." This is a timely and potentially transformative perspective shift, especially given industry trends toward modularity (IBM multi-chip, IonQ/Pasqal acquisitions of interconnect companies).
Practical implications: The concrete resource estimates (381k-190k qubits for RSA-2048) are within range of industry 5-10 year roadmaps, making the results immediately relevant for hardware planning. The decomposition into functional modules provides clear development targets for different hardware teams.
Broader influence: The requirement-driven framework (Table I) serves as a useful taxonomy for the field. The demonstration that code heterogeneity (surface codes for processing, qLDPC for memory) yields ~2× additional qubit reduction supports the emerging view that no single QEC code is optimal for all functions.
4. Timeliness & Relevance
This paper addresses a critical gap at a pivotal moment. With Google, IBM, Quantinuum, and others demonstrating QEC below threshold, and DARPA's HARQ program explicitly soliciting heterogeneous architectures, this work is exceptionally well-timed. The "tyranny of numbers" framing connects quantum scaling challenges to well-understood classical precedents, making the architectural argument accessible to a broad audience.
5. Strengths & Limitations
Key strengths:
Notable weaknesses:
Overall Assessment
This is a significant architectural contribution that brings much-needed systems-level thinking to fault-tolerant quantum computing. The quantitative framework is thorough, and the results are compelling within the stated assumptions. However, the practical realizability of the full architecture—particularly the quantum bus and memory interfaces—remains uncertain, and the comparison baseline could be more competitive. The paper's greatest value may be in establishing heterogeneous architecture as a legitimate and quantitatively supported design paradigm, rather than in the specific numerical claims.
Generated Apr 9, 2026
Comparison History (224)
Paper 2 likely has higher scientific impact due to a broadly applicable, theoretically optimal result: a query-optimal classical-shadow protocol for unitary channels achieving Heisenberg scaling, with matching lower bounds and a closure of the parallel-vs-sequential tomography gap. This advances fundamentals of quantum learning/tomography and propagates across many subareas (Hamiltonian learning, amplitude estimation, process tomography, shallow-circuit learning). Paper 1 is highly relevant and practical for fault-tolerant architecture, but its impact is more domain-specific and contingent on hardware/assumption realism, whereas Paper 2 provides general, reusable theory with strong rigor and wide downstream use.
Paper 2 addresses one of the most significant bottlenecks in fault-tolerant quantum computing: physical qubit overhead. By demonstrating a 138x reduction in required qubits and detailing practical resource estimates for factoring RSA-2048, it bridges the gap between hardware limitations and QEC code requirements. While Paper 1 presents an excellent experimental advance in materials for quantum interconnects, Paper 2 offers a systemic architectural breakthrough with broad, immediate implications for scaling quantum computers across various hardware platforms.
Paper 1 likely has higher scientific impact due to its broad, system-level architectural advance for fault-tolerant quantum computing, including detailed resource accounting, a full heterogeneous microarchitecture, and a compiler demonstrated at 1,000 logical qubits. The claimed 138× physical-qubit reduction and concrete RSA-2048 resource estimates directly influence roadmaps for scalable quantum hardware and cross-cut architecture/QEC/compiler communities. Paper 2 is a strong applied demonstration (20 Mbps SDI randomness amplification) with clear near-term cryptographic relevance, but its scope is narrower and its broader field-spanning implications are likely smaller than Paper 1’s.
Paper 2 addresses a critical bottleneck in quantum computing, offering a massive 138x reduction in physical qubit requirements. This practical architectural breakthrough accelerates the timeline for fault-tolerant quantum computing and applications like RSA factorization, promising broader and more immediate real-world impact across industry and academia compared to the profound, yet predominantly theoretical, foundational physics insights of Paper 1.
Paper 2 addresses a critical bottleneck in quantum computing—the enormous physical qubit overhead for fault-tolerant computation—achieving up to 138x reduction through heterogeneous architectures. This has immediate, broad practical impact on quantum computing hardware roadmaps, compiler design, and algorithm implementation. The concrete RSA-2048 factoring estimates (381k-190k qubits) provide actionable benchmarks for the entire field. While Paper 1 makes an elegant contribution unifying quantum metrology and cryptography, Paper 2's architectural framework, compiler tooling, and dramatic resource reductions address a more fundamental and widely impactful challenge facing quantum technology development.
Paper 2 likely has higher impact because it demonstrates experimental, fault-tolerant logical operations (lattice surgery, logical Bell state, logical algorithm execution, and magic-state injection/teleportation) on a superconducting surface-code processor—an essential, timely milestone toward scalable quantum computing. Its results are immediately actionable for hardware roadmaps and broadly relevant across quantum error correction, device engineering, and near-term FTQC demonstrations. Paper 1 is innovative and potentially influential for architecture/resource estimation, but its impact depends on assumptions/models and future hardware realization, whereas Paper 2 provides concrete experimental validation.
Paper 1 likely has higher impact: it delivers a system-level, end-to-end heterogeneous fault-tolerant quantum computing architecture with detailed resource accounting, compiler/tooling, and concrete RSA-2048 estimates on realistic coupling assumptions—highly timely for scaling roadmaps and broadly relevant across quantum architecture, compilation, and hardware/QEC co-design. Paper 2 is novel and theoretically strong (provable separation for CV reservoir computing with Kerr feedback) but targets a narrower subcommunity and its real-world advantage depends on practical Kerr strength, loss engineering, and measurement-time tradeoffs.
Paper 2 presents a complete heterogeneous quantum computing architecture with a full compiler stack, demonstrating massive (138x) reductions in physical qubit overhead for practical algorithms like RSA-2048 factoring. Its broader scope—bridging hardware, architecture, QEC, and compilation across subsystems at 1000+ logical qubit scale—gives it wider impact across quantum computing. While Paper 1 makes important contributions to logical processing in QLDPC codes, it addresses a more specialized subproblem. Paper 2's concrete resource estimates for real algorithms and its hardware-agnostic framework make it more immediately impactful for the field.
Paper 2 presents a comprehensive heterogeneous quantum computing architecture with a full compiler stack, achieving dramatic (138x) reductions in physical qubit requirements. It bridges the gap between hardware and QEC theory, provides concrete RSA-2048 factoring estimates, and introduces architectural concepts applicable across the entire field. While Paper 1 makes an important contribution to Clifford+T synthesis with practical implications for Trotterization, Paper 2 has broader impact spanning architecture, compilation, error correction, and resource estimation, addressing a more fundamental bottleneck in scaling quantum computing.
Paper 2 presents a broad, system-level heterogeneous architecture and compiler that bridges physical hardware and QEC codes, rather than optimizing a specific code like Paper 1. By introducing specialized processing modules and supporting diverse hardware/codes (including qLDPC), it demonstrates massive qubit reductions (138x) for benchmark algorithms like RSA-2048. Its agnostic, comprehensive framework provides wider applicability and a more scalable path forward for quantum architecture design.