SiGe/Si(111)/SiGe heterostructure for Si spin qubits with electrons confined in L valley of conduction band
Takafumi Tokunaga, Hiromichi Nakazato
Abstract
In Si(111) crystals, a strong biaxial tensile strain applied within the (111) plane is considered to shift the lowest energy point of the conduction band from the valley to the L valley. Electrons confined in this L valley experience a splitting of their quadruply degenerate energy levels into an undegenerate single-level ground state (L1) and a triply degenerate excited state (L3). The energy of the single-level ground state is sufficiently low relative to the energies of the L3 valley and the valley, making it optimal as a two-level system for a qubit. Using deformation potential theory and incorporating quantum effects from electron confinement in the SiGe/Si(111)/SiGe structure, we determine the value of the biaxial tensile strain causing the shift of the conduction band energy minimum from the valley to the L valley, along with the corresponding Ge concentration. We also calculate the critical thickness for the plastic relaxation of the Si quantum well under this large biaxial tensile strain and examine the feasibility of realizing it as a SiGe/Si(111)/SiGe heterostructure.
AI Impact Assessments
(3 models)Scientific Impact Assessment
Core Contribution
This paper proposes a novel approach to address the valley degeneracy problem in silicon spin qubits by using a SiGe/Si(111)/SiGe heterostructure that confines electrons in the L valley rather than the conventional Δ valley. The key insight is that by applying strong biaxial tensile strain (>3.9%) within the (111) plane of a thin Si layer sandwiched between high-Ge-concentration SiGe layers, the conduction band minimum shifts from the Δ valley to the L valley. In the L valley, the fourfold degeneracy splits into a non-degenerate ground state (L1) and a triply degenerate excited state (L3), eliminating the problematic pseudo-degeneracy that plagues conventional Si(001)-based qubits.
The fundamental problem being addressed — unstable valley splitting in Si/SiGe quantum dots on (001) substrates — is a well-recognized bottleneck in silicon quantum computing. The valley splitting in conventional structures varies unpredictably between 20–300 μeV due to atomic-scale interface roughness, interfering with the Zeeman-split two-level qubit system. The proposed L-valley approach would eliminate this issue entirely by providing a non-degenerate ground state with the nearest competing valley ~72 meV higher, far exceeding typical Zeeman splitting energies.
Methodological Rigor
The theoretical framework combines deformation potential theory (first-order linear and second-order nonlinear terms), quantum confinement calculations in a finite-barrier well potential, and critical thickness analysis using the People-Bean model. The methodology is sound but relatively straightforward:
Strengths in methodology:
Weaknesses in methodology:
Potential Impact
If experimentally validated, this proposal could represent a paradigm shift in silicon spin qubit architecture. The elimination of valley degeneracy problems would remove one of the most significant obstacles to scaling silicon quantum computers. The additional claim of very high electron mobility (effective mass ~0.12m₀ in-plane) in the L valley could have applications beyond quantum computing, potentially in high-speed FET technology.
However, the practical impact is tempered by several factors:
1. Fabrication challenges are formidable. Growing coherent Si films under ~4% tensile strain on nearly-pure Ge requires preventing Stranski-Krastanov island growth and Ge interdiffusion — challenges the authors acknowledge but do not resolve.
2. Departure from mainstream CMOS. Si(111) substrates and near-pure Ge buffer layers represent a significant departure from standard Si(001) CMOS technology, potentially undermining the CMOS-compatibility advantage of silicon qubits.
3. No experimental validation. The paper is purely theoretical with no experimental demonstration or collaboration with experimentalists, which limits its immediate influence.
4. Integration concerns. The authors note that qubit devices would need separate fabrication from CMOS, adding complexity.
Timeliness & Relevance
The paper addresses a genuinely pressing problem. Recent high-profile publications (Nature 2024-2025) continue to highlight valley splitting variability as a major challenge for silicon qubit scaling. The timing is relevant given the recent push toward large-scale silicon quantum processors by Intel, Google, and others. However, the community has been primarily pursuing solutions within the Si(001) paradigm (Ge concentration oscillations, interface engineering), making this (111)-based proposal somewhat orthogonal to mainstream efforts.
Strengths & Limitations
Key Strengths:
Notable Limitations:
Overall Assessment
This paper presents an intellectually interesting theoretical proposal that, if validated, could offer a fundamentally different approach to silicon spin qubits. However, it remains at an early conceptual stage — a theoretical feasibility study without experimental support or detailed first-principles validation. The extreme fabrication requirements and departure from standard silicon processing significantly constrain near-term practical impact. The work would benefit substantially from ab initio band structure calculations of the specific heterostructure and from collaboration with experimental groups capable of attempting the proposed growth.
Generated Apr 16, 2026
Comparison History (39)
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