Hardware-Efficient Erasure Qubits With Superconducting Transmon Qutrits
Bao-Jie Liu, Ying-Ying Wang, Yu-Xin Wang, Manthan Badbaria, Shruti Puri, Chen Wang
Abstract
Quantum error correction using erasure qubits offers higher fault-tolerant thresholds and improved scaling by converting dominant physical errors into detectable erasures. In superconducting circuits, erasure qubits can be constructed using the dual-rail approach, which, however, requires additional qubit-count overhead and tailored coupling elements. Here, we demonstrate a hardware-efficient scheme that operates transmon qutrits as erasure qubits, which is compatible with standard superconducting circuit-QED hardware. The logical states and are represented by the ground and second excited states, while the dominant relaxation errors can be detected via an ancilla qubit using a microwave-activated two-qutrit SWAP gate. We demonstrate a logical qubit lifetime exceeding , post-selected with repeated mid-circuit erasure detection, which is ten times longer than the time of the transmon physical qubit. Coherence times beyond are achieved using dynamical decoupling. Single-qubit gate operations reach average Clifford gate infidelity on the order of . We further demonstrate dual-purposing an ancilla qubit for both erasure detection and parity checking, showing heralded generation of Bell states between erasure qubits. These results suggest that mainstream architectures of transmon qubit arrays may already be capable of implementing erasure-based QEC strategies for hardware-efficient fault-tolerant quantum computing.
AI Impact Assessments
(3 models)Scientific Impact Assessment
1. Core Contribution
This paper demonstrates a hardware-efficient erasure qubit scheme using the ground (|g⟩) and second excited (|f⟩) states of standard superconducting transmon qutrits, an approach previously proposed theoretically (the "g–f erasure qubit" by Kubica et al., 2023) but not experimentally realized with transmons until now. The key innovation is that dominant relaxation errors (|f⟩→|e⟩) manifest as detectable leakage to the intermediate |e⟩ state, which can be flagged via an ancilla-assisted microwave-activated SWAP gate. This contrasts with the prevailing dual-rail approach to superconducting erasure qubits, which requires two physical qubits per logical qubit plus dedicated ancillary circuitry.
The central experimental achievements are: (1) logical T₁ exceeding 500 μs via repeated mid-circuit erasure detection—10× longer than the bare transmon T₁ (~55 μs); (2) coherence times >300 μs with dynamical decoupling; (3) single-qubit Clifford gate infidelity ~7.6×10⁻⁴ with post-selection; and (4) heralded Bell state generation between two g–f erasure qubits using a dual-purpose ancilla for both erasure detection and parity checking.
2. Methodological Rigor
The experimental methodology is thorough and well-characterized. The erasure detection scheme using a four-wave-mixing (FWM) SWAP gate is carefully motivated by spectroscopic analysis showing that alternative approaches (flux-based iSWAP, CZ gates) suffer from spectral crowding due to weak transmon anharmonicity. The choice of operating point near but away from the |ee⟩-|0_Lf⟩ avoided crossing is justified through energy-level analysis.
Error budgets are detailed and internally consistent. The bit-flip lifetime analysis identifies three dominant contributions (cascaded decay, false negatives, pulse errors) totaling ~2.8×10⁻³ per cycle, matching the measured 3.0×10⁻³. The ~13:1 ratio of erasure-to-Pauli error rates confirms the desired error hierarchy. False positive (~2.0-2.4%) and false negative (~6-8%) rates are carefully decomposed and attributed to specific physical mechanisms. Numerical gate simulations agree reasonably with experimental benchmarking results.
However, several limitations deserve note. The ancilla coherence time away from its sweet spot (0.7–1 μs) is a significant bottleneck, contributing substantially to false negative rates. The Bell state fidelities (0.85–0.93) are modest, and the authors acknowledge that the parity experiment was conducted during a period of reduced coherence. The coherence stability data (Fig. S13) shows noticeable fluctuations, suggesting sensitivity to TLS defects and flux noise.
3. Potential Impact
The most significant practical implication is compatibility with existing transmon hardware. Unlike dual-rail erasure qubits requiring specialized coupling elements and doubling the qubit count for logical encoding, the g–f scheme works on "industry-standard flux-tunable transmon qubits without any special design of circuit parameters." This dramatically lowers the barrier to adoption—existing multi-qubit processors could, in principle, be repurposed for erasure-based QEC without fabrication changes.
The dual-purposing of ancilla qubits for both erasure detection and stabilizer checking is a particularly impactful concept. In a surface code architecture, this means the syndrome-extraction qubits already present could simultaneously perform erasure monitoring, potentially avoiding the factor-of-three hardware overhead that dual-rail approaches incur. Preliminary analyses referenced (Ref. [43]) suggest surface codes with this "delayed" erasure detection retain advantages in threshold and scaling.
The work could influence quantum processor design philosophy by suggesting that the transmon's multilevel structure—often viewed as a liability—can be systematically exploited. This connects to a broader trend in qutrit/qudit computing.
4. Timeliness & Relevance
This work arrives at a critical moment. The quantum computing community is intensely focused on the path to fault tolerance, with Google's recent below-threshold surface code demonstration (Ref. [8]) highlighting the enormous physical qubit overhead of conventional approaches. Erasure qubits offer a compelling route to reduce this overhead, and the dual-rail superconducting implementation has generated significant excitement (Refs. [29-36]). However, the hardware cost of dual-rail encoding is a recognized concern (Ref. [19]). This paper addresses precisely this bottleneck.
The concurrent independent demonstration using integer fluxonium (Ref. [62]) confirms the timeliness and community interest in g–f encoding beyond dual-rail approaches.
5. Strengths & Limitations
Key Strengths:
Notable Limitations:
Additional Observations
The paper bridges an important gap between theoretical proposals and practical implementation. The path to improvement is clear: Purcell filters for faster readout, optimized circuit parameters to reduce measurement-induced transitions, and improved qutrit gate techniques. The scalability argument is compelling but remains to be validated at larger scales where crosstalk and frequency crowding become more challenging for qutrits than for qubits.
Generated Apr 13, 2026
Comparison History (198)
Paper 1 has higher near-term scientific impact: it demonstrates a hardware-compatible, experimentally validated route to erasure-based QEC in mainstream transmon platforms, with concrete performance metrics (logical T1 extension, mid-circuit detection, gate infidelity ~1e-4) and direct relevance to fault-tolerant scaling. Its applications to quantum computing architectures are immediate and broad across quantum engineering and QEC. Paper 2 is conceptually novel and could be foundational, but its impact is more speculative, likely theory-heavy, and depends on uptake and experimental/technological realizations of “febits.”
Paper 2 demonstrates lattice-surgery logical operations on surface codes—a critical milestone for scalable fault-tolerant quantum computing. It implements multiple key primitives (logical Bell states, a logical algorithm, magic-state injection, and non-Clifford gates) on a practical architecture, directly addressing the path to fault-tolerant quantum advantage. While Paper 1 presents an innovative hardware-efficient erasure qubit scheme with impressive coherence improvements, Paper 2's demonstration of full logical-level operations with lattice surgery has broader and more immediate impact on the field's central goal of scalable quantum error correction.
Paper 2 demonstrates a practical, hardware-efficient erasure qubit scheme using existing transmon technology—the dominant superconducting qubit platform. Achieving 10x T1 improvement and ~10^-4 gate infidelity with standard circuit-QED hardware has immediate implications for fault-tolerant quantum computing, as it suggests existing transmon arrays can implement erasure-based QEC without architectural overhaul. This directly addresses the critical bottleneck of quantum error correction scalability. Paper 1, while theoretically elegant in proving resource separations for quantum reservoir computing, addresses a more niche application with less immediate experimental validation and narrower community impact.
Paper 1 presents an experimental demonstration of erasure qubits on standard superconducting hardware, achieving a 10-fold increase in lifetime. Its compatibility with mainstream architectures offers immediate, practical applications for improving current quantum devices. While Paper 2 addresses crucial long-term scaling challenges for QLDPC codes, Paper 1's experimental breakthrough on existing hardware is likely to have a more immediate and widespread scientific impact across the quantum computing community.
Paper 2 offers a fundamental algorithmic breakthrough that drastically reduces T-gate overhead for small-angle rotations, a major bottleneck in fault-tolerant quantum compilation. Its results are hardware-agnostic and will broadly impact resource estimates for numerous quantum algorithms, especially Hamiltonian simulation. Paper 1 is a strong experimental demonstration but is limited in breadth to superconducting transmon architectures.
Paper 2 likely has higher impact due to its broad, architecture-level advance: a denser planar surface code with substantially improved encoding rate, space/time overheads, and concrete end-to-end resource estimates for utility-scale algorithms (e.g., FeMoco) under circuit-level noise. This is timely and widely applicable across quantum computing platforms implementing 2D nearest-neighbor layouts, influencing fault-tolerant design, compilation, and hardware roadmaps. Paper 1 is experimentally strong and novel for transmon-qutrit erasure detection, but its applicability is more platform-specific and may require further integration into full QEC stacks to match Paper 2’s field-wide impact.
Paper 2 likely has higher impact because it delivers an experimentally demonstrated, hardware-compatible path to erasure-based QEC in mainstream superconducting transmon platforms, with concrete performance metrics (10× T1 extension, ~1e-4 Clifford infidelity, mid-circuit detection, Bell-state generation, ancilla dual-purposing). This is timely and directly relevant to near-term fault-tolerance roadmaps, with broad applicability across superconducting architectures. Paper 1 is conceptually novel for open-system simulation via partial QEC, but appears more theoretical and its practical uptake depends on future implementations and benchmarking.
Paper 1 demonstrates a hardware-efficient erasure qubit scheme using standard transmon hardware, achieving 10x improvement in logical qubit lifetime and high-fidelity gates. This has immediate practical impact for fault-tolerant quantum computing, as it shows existing superconducting qubit arrays can implement erasure-based QEC without additional hardware overhead. Paper 2 provides important theoretical convergence guarantees for SDP hierarchies applied to Pauli Hamiltonians, but its impact is more specialized within Hamiltonian complexity theory. Paper 1's experimental results and direct applicability to mainstream quantum computing architectures give it broader and more timely impact.
Paper 1 addresses a critical bottleneck in quantum computing—error correction—by demonstrating a hardware-efficient approach to erasure qubits on widely used superconducting transmon architectures. By achieving a 10x improvement in T1 lifetimes without requiring complex hardware overhead, it offers immediate, highly scalable implications for the leading quantum computing platform. While Paper 2 presents a novel approach to scalable quantum light sources, Paper 1's direct and practical impact on overcoming fault-tolerance challenges in mainstream quantum hardware gives it a broader and more urgent scientific impact.
Paper 2 demonstrates experimental results on existing mainstream hardware (transmon qutrits), showing a 10x improvement in logical T1 lifetime and compatibility with standard circuit-QED setups. Its practical immediacy—requiring no new hardware paradigms—gives it broader near-term impact across the superconducting quantum computing community. Paper 1, while theoretically valuable in proposing QND measurements as a CNOT alternative for biased-noise platforms, is primarily a theoretical/simulation contribution. Paper 2's experimental validation of erasure qubits on widely deployed transmon arrays has stronger potential to influence near-term fault-tolerant QEC implementations.