From GDSII to Wafer: EDA Design Flow and Data Conversion for Wafer-Scale Manufacturing of Superconducting Quantum Chips
Ling Qiao, Fumin Luo, Qinglang Guo
Abstract
Superconducting quantum computing is advancing toward the thousand- and even million-qubit regime, making wafer-scale fabrication an essential pathway for achieving large-scale, cost-effective quantum processors. This manufacturing paradigm imposes new requirements on quantum-chip electronic design automation (Q-EDA): design tools must not only generate layouts (GDSII files) that satisfy quantum-circuit physical constraints but also ensure that the design data can be seamlessly converted into a complete set of manufacturing files executable by a wafer foundry, thereby enabling reliable translation from design intent to physical chip. This paper focuses on this critical data-conversion pipeline and presents a systematic treatment of the Q-EDA technology stack for wafer-scale fabrication. Starting from GDSII as the single authoritative data source, we analyze the key stages including process-design-kit (PDK)-based design rule checking (DRC), layout-versus-schematic (LVS) verification, design for manufacturability (DFM) optimization, wafer layout planning, and mask data preparation (MDP). We describe the concrete architecture of a Q-EDA system, present nine quantum-specific DRC rules together with their physical underpinnings and a multi-layer process stack model, and benchmark the manufacturing data-flow coverage of mainstream Q-EDA tools. Finally, we discuss the core challenges and future directions in this field.
AI Impact Assessments
(3 models)Scientific Impact Assessment
Core Contribution
This paper addresses the data-conversion pipeline required to translate superconducting quantum chip designs (in GDSII format) into complete manufacturing files suitable for wafer-scale fabrication. The authors present a four-layer Q-EDA system architecture, define nine quantum-specific design rule checking (DRC) rules with physical justifications, describe a multi-layer process stack model for Nb/Al-AlOx superconducting processes, and benchmark their rule set against the CMC Microsystems PDK white paper. The paper also surveys existing Q-EDA tools (Origin Pilot, EDA-Q, Qiskit Metal, KQCircuits, GDSFactory) and identifies a "strong front-end, weak back-end" gap in the ecosystem.
The central problem—bridging the gap between design layout generation and foundry-ready manufacturing file preparation for superconducting quantum chips—is a genuine engineering need as the field scales toward wafer-level production. The paper correctly identifies that most existing Q-EDA tools focus on layout generation and simulation but neglect DFM, wafer mapping, and mask data preparation (MDP).
Methodological Rigor
The paper's methodological rigor is limited in several important respects:
Shallow prototype validation. The experimental validation consists of running DRC checks on a 28-component test chip (4 qubits) in 0.23 ms and a 50-qubit stress test (1,016 geometric primitives) in 2.94 ms. These are toy-scale demonstrations. A serious validation would involve hundreds or thousands of qubits, realistic wafer-scale layouts with millions of geometric primitives, and comparison against industry-standard verification tools (e.g., Calibre, IC Validator). The claim of O(n) scaling based on two data points is not rigorous.
No fabrication validation. The paper presents no evidence that the generated manufacturing files were actually used to fabricate devices on a wafer line. Without silicon (or niobium) validation, the claim that this pipeline enables "reliable translation from design intent to physical chip" remains unsubstantiated.
DRC rules lack novelty. The nine DRC rules presented (Table I) are reasonable engineering guidelines, but they represent well-known constraints from microwave engineering and superconducting device fabrication. The thresholds (e.g., CPW gap ≥ 3 μm, JJ overlap ± 50 nm) are standard values from the literature. The benchmarking against CMC PDK (Table II) shows minor threshold differences rather than fundamentally new rule categories.
Missing critical details. The paper mentions LVS, ERC, DFM, OPC, and MDP as stages in the pipeline but provides minimal detail on their actual implementation. For instance, OPC for superconducting quantum chips is mentioned but not demonstrated. The wafer mapping module is described conceptually but not validated. The MDP stage—arguably the most critical for the paper's stated contribution—is described only at the level of general concepts (fracturing, reticle generation, job deck generation) without implementation specifics.
Potential Impact
The paper addresses a real industrial need. As companies like IMEC, IBM, and Google push toward wafer-scale superconducting quantum chip fabrication on 300 mm lines, standardized design-to-manufacturing pipelines will become essential. However, the paper's impact is limited by:
1. The prototype is too early-stage to serve as a practical tool for the community. Sub-millisecond DRC on 28 components is not a meaningful benchmark for industrial adoption.
2. No open-source release or reproducibility information is provided for the Q-EDA system, limiting community adoption.
3. The survey component (Table IV comparing tools) provides useful context but is relatively superficial, with many entries marked "planned" or "not supported" without deeper analysis.
The paper's most useful contribution may be as a pedagogical roadmap—clearly laying out the stages from GDSII to foundry-ready files and identifying where quantum-specific considerations differ from classical CMOS flows. For researchers entering this space, this framing could be valuable.
Timeliness & Relevance
The paper is timely. IMEC's 2024 Nature paper demonstrating superconducting transmon qubits on 300 mm CMOS lines validates that wafer-scale quantum chip fabrication is becoming practical. The need for mature Q-EDA back-end tools is real and growing. However, the paper's contribution to solving this problem is more architectural/conceptual than technical/implementational.
Strengths
Limitations
Overall Assessment
This paper serves primarily as a roadmap and overview of the Q-EDA back-end pipeline for superconducting quantum chip wafer-scale fabrication. While it addresses a genuine and timely need, the technical contributions are incremental—the DRC rules codify known constraints, the system architecture follows standard EDA patterns, and the prototype validation is minimal. The paper would benefit significantly from either (a) deeper algorithmic contributions in one or more pipeline stages, (b) fabrication validation demonstrating the pipeline's end-to-end effectiveness, or (c) an open-source release enabling community adoption and validation.
Generated Apr 19, 2026
Comparison History (42)
Paper 2 introduces a novel exactly solvable theoretical model revealing qualitatively new physics—quantum entanglement between spin and mechanical rotation—that fundamentally revises the classical understanding of the Barnett and Einstein–de Haas effects. This has broad implications across quantum mechanics, spintronics, and quantum information. Paper 1, while practically useful for superconducting quantum chip manufacturing, is primarily an engineering workflow description for EDA tools rather than a fundamental scientific contribution, limiting its broader scientific impact despite its industrial relevance.
Paper 2 likely has higher scientific impact: it targets a timely bottleneck for scaling superconducting quantum hardware—end-to-end, foundry-executable wafer-scale manufacturing workflows. Its contributions (system architecture, quantum-specific DRC rules with physical basis, process stack model, and benchmarking of mainstream Q-EDA coverage) are directly actionable for industry and can standardize practices across toolchains, affecting large efforts toward million-qubit systems. Paper 1 is novel and useful, but as a heuristic optimization method its impact may be narrower and more incremental relative to the broad manufacturing/EDA infrastructure needs.
Paper 1 addresses a critical infrastructure need for scaling superconducting quantum computing to thousands/millions of qubits through wafer-scale fabrication, presenting systematic EDA methodology with quantum-specific design rules and process models. This has broader impact as it enables the entire quantum computing hardware ecosystem. Paper 2 presents a hybrid quantum optimization framework for CVRP that explicitly disclaims quantum advantage, offering incremental improvements to a specific combinatorial problem. Paper 1's contributions to quantum chip manufacturing infrastructure have more foundational and far-reaching impact across the field.
Paper 1 has higher potential impact due to its broader, enabling scope: it addresses the end-to-end Q-EDA data-conversion and verification pipeline required for wafer-scale superconducting quantum chip manufacturing, including quantum-specific DRC rules and an architecture benchmarked against existing tools. This is timely for scaling to 1000+ qubits and could influence tooling standards and multiple foundry/design ecosystems. Paper 2 is valuable but narrower: an incremental materials/process improvement with modest performance gains, likely impacting a more limited set of device implementations.
Paper 2 is more novel and broadly impactful: it advances a central, difficult problem in quantum information theory by providing new single-letter characterizations of one-way distillable entanglement for explicit non-degradable, non-PPT state families, introducing new conditions and additivity/stability results with links to quantum channel capacity. These are rigorous, general theoretical contributions likely to be reusable across QIT and related fields. Paper 1 is timely and practically important for superconducting quantum chip manufacturing, but is more engineering/systematization-focused and narrower in field breadth.
Paper 2 proposes a novel quantum simulation scheme for the Motzkin spin chain using Rydberg atoms, bridging theoretical mathematics with experimental quantum physics. It connects to fundamental topics (topological phases, AdS/CFT, area-law violations) and offers a concrete experimental pathway using programmable Rydberg simulators. This has broader scientific impact across condensed matter, quantum information, and high-energy physics. Paper 1, while practically useful for superconducting quantum chip manufacturing, is more of an engineering/EDA workflow contribution with narrower impact primarily in quantum hardware fabrication methodology.
Paper 2 offers a more novel, broadly relevant physics result: a direct, experimentally demonstrated connection between qubit coherence/decoherence mechanisms and measurable phase statistics of emitted radiation in an open waveguide. This is methodologically rigorous (single-shot heterodyne, quantitative links to relaxation and dephasing) and likely impactful across quantum optics, open quantum systems, and superconducting qubits, with clear utility for characterization and diagnostics. Paper 1 is timely and practically important for scaling superconducting QPUs, but is more engineering/process-integration focused and may have narrower scientific reach beyond the quantum-EDA/manufacturing community.
Paper 2 has higher likely impact due to strong real-world applicability and timeliness: wafer-scale superconducting quantum chip manufacturing is a key bottleneck for scaling to large qubit counts. A systematic, end-to-end Q-EDA-to-foundry data conversion pipeline (DRC/LVS/DFM/MDP) can be directly adopted by industry and multiple research groups, influencing tooling, standards, and fabrication reliability across quantum hardware and EDA communities. Paper 1 is novel and scientifically interesting for non-Hermitian quantum simulation, but near-term experimental deployment and broad cross-field adoption may be more limited.
Paper 2 addresses a fundamental and broadly applicable problem in quantum machine learning—how numerical data encoding affects generative model performance—and proposes a practical, generalizable solution (Gray-code encoding) with demonstrated improvements. This has wider cross-disciplinary impact spanning quantum computing, machine learning, and data science. Paper 1, while valuable for the superconducting quantum chip manufacturing community, is more narrowly focused on EDA tooling and data conversion pipelines, serving a specialized engineering audience with less potential for broad scientific influence.
Paper 1 introduces a novel theoretical framework for pixel-translation-equivariant QCNNs with rigorous mathematical characterization, trainability guarantees against barren plateaus, and a constructive design methodology. It addresses a fundamental mismatch in quantum machine learning and contributes broadly to quantum computing theory. Paper 2, while practically useful for superconducting quantum chip manufacturing, is more of an engineering systems paper describing an EDA pipeline and design rules—important but incremental and narrower in scope. Paper 1's theoretical contributions have broader potential to influence multiple research directions in quantum ML.
Paper 2 addresses a critical infrastructure challenge for scaling superconducting quantum computing to thousands/millions of qubits—wafer-scale manufacturing EDA workflows. This is highly timely as the field transitions toward large-scale processors, and no systematic treatment of this pipeline previously existed. It establishes foundational design rules and toolchain architecture that will be broadly adopted. Paper 1, while combining quantum computing with deep learning for error mitigation on Frenkel excitons, addresses a more niche application with incremental advances in both the physics and the error mitigation methodology.
Paper 2 presents a novel open-source implementation of the ACSE method for computing all-electron correlation in molecules, addressing a fundamental challenge in quantum chemistry. It offers broad applicability across molecular systems (main group, transition metals, ground/excited states) and the open-source nature maximizes community adoption. Paper 1, while addressing an important engineering challenge in quantum chip manufacturing, is more narrowly focused on a specific manufacturing pipeline with incremental contributions to EDA workflows. Paper 2's methodological innovation in electronic structure theory has broader scientific impact across chemistry, materials science, and physics.
Paper 1 offers a substantive methodological advance in open-quantum-system simulation: generalizing TEMPO/tensor-network influence functionals to multiple non-commuting system-bath couplings and addressing Trotter-error handling for long-time convergence. This is novel, broadly useful across quantum optics, condensed matter, chemistry, and quantum thermodynamics, and can enable new quantitative studies of structured environments. Paper 2 is timely and valuable for engineering practice in superconducting quantum chip manufacturing workflows, but is more systems/implementation-focused with narrower scientific-methodological novelty and likely less cross-disciplinary theoretical impact.
Paper 2 likely has higher impact: it proposes a new algorithmic framework (ADAPT-VMPE) with claimed theoretical guarantees, polynomial complexity, and demonstrations up to 100 qubits on a chemically and medically relevant strongly correlated system. This combination of novelty, scalability claims, and cross-domain application (quantum algorithms, computational chemistry, potentially drug/therapy design) gives broader and more timely reach. Paper 1 is valuable engineering infrastructure for superconducting Q-EDA and manufacturing readiness, but its impact is narrower to a specific hardware stack and appears more integrative/systematizing than fundamentally new.
Paper 2 is likely to have higher scientific impact due to direct timeliness and applicability: it addresses wafer-scale manufacturing workflows for superconducting quantum chips, a near-term bottleneck for scaling to large qubit counts. It provides a concrete systems/EDA pipeline, quantum-specific DRC rules, benchmarking of existing tools, and foundry-facing data preparation—outputs that can be adopted by industry and research groups, influencing standards and practice. Paper 1 is conceptually novel and rigorous in mathematical physics/quantum information, but its impact is more specialized and less immediately actionable across the broader quantum engineering ecosystem.
Paper 1 offers a more novel, broadly relevant theoretical contribution: a rigorous information-theoretic scaling law linking quantum-state structure (mutual information) to neural quantum state capacity, with provable results and cross-task validation (tomography, ground/thermal learning) and architecture comparisons. This can influence quantum many-body theory, machine learning, and tensor-network/NQS research. Paper 2 is timely and valuable for engineering practice in superconducting quantum manufacturing, but it is more workflow/systematization-focused and likely narrower in scientific generality and methodological novelty, with impact concentrated in Q-EDA and fabrication tooling.
Paper 1 addresses a fundamental question in quantum information theory about information retention in random circuits, discovering a universal phase transition and exact characterizations. This has broad theoretical impact across quantum computing, many-body physics, and thermalization. Paper 2 is a practical engineering contribution to quantum chip manufacturing EDA workflows—important for industry but narrower in scope, more incremental (adapting classical EDA concepts), and primarily a systems/process description rather than a discovery of new scientific principles.
Paper 1 targets a timely bottleneck for scaling superconducting quantum processors: wafer-scale manufacturability and the end-to-end Q-EDA data pipeline from GDSII to foundry-ready mask prep. By formalizing conversion stages (DRC/LVS/DFM/MDP), introducing quantum-specific DRC rules, and benchmarking tool coverage, it can directly influence industrial practice, standardization, and reproducible fabrication—impacting many groups and enabling large-scale deployment. Paper 2 is methodologically solid and novel in simplifying H-infinity coherent feedback synthesis, but its scope is narrower (linear quantum optics/control community) and less immediately tied to near-term scaling pathways.
Paper 2 has higher potential impact due to its broader applicability and timeliness: wafer-scale superconducting chip manufacturing and Q-EDA infrastructure are key bottlenecks for scaling to large qubit counts. It proposes a systematic, end-to-end design-to-foundry data conversion pipeline (GDSII→PDK/DRC/LVS/DFM→MDP), quantum-specific DRC rules, tool benchmarking, and an architecture that can influence both academia and industry across quantum hardware, EDA, and manufacturing. Paper 1 is useful but narrower (H2 VQE benchmarking on IBM devices) and likely has limited cross-field reach and longer-term influence.
Paper 1 targets an urgent bottleneck for scaling superconducting quantum processors: wafer-scale manufacturability and the EDA-to-foundry data pipeline. Its contributions (end-to-end architecture, quantum-specific DRC rules with physical justification, process stack modeling, and benchmarking of current tools) are directly actionable, likely to influence industrial workflows, standards/PDKs, and enable faster iteration across many labs and fabs. Paper 2 is conceptually elegant and potentially impactful within quantum thermodynamics, but is more specialized and its near-term applicability and adoption are less certain than a manufacturing-enabling Q-EDA framework.